jon fc968c867f PC compression scheme for the instruction fetch pipeline. ...

Store the upper bits of the PC in a table and only handle indices and
lsbs in the main pipeline.
This eliminates redundancy between PCs and predicted PCs, and even more
between fragments of instructions.

2021-01-14 11:41:11 +00:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Support for stat counters from the tag controller.

2020-12-17 12:38:52 +00:00

CPU

Add counter support to ITLB.

2020-12-17 17:57:43 +00:00

Debug_Module

Port to internal AXI interfaces for the debug module.

2020-12-17 15:02:05 +00:00

ISA

Replace enums-for-constants with structs wrapping a plain Bit#(n)

2020-07-15 03:16:24 +01:00

PLIC

PLIC: Update comment after previous commit

2020-12-21 13:37:01 +00:00

RISCY_OOO

PC compression scheme for the instruction fetch pipeline.

2021-01-14 11:41:11 +00:00