jon fc968c867f PC compression scheme for the instruction fetch pipeline. ...

Store the upper bits of the PC in a table and only handle indices and
lsbs in the main pipeline.
This eliminates redundancy between PCs and predicted PCs, and even more
between fragments of instructions.

2021-01-14 11:41:11 +00:00

..

coherence/src

Implement a couple Cache counters in the LLCache.

2020-12-15 18:16:21 +00:00

connectal

Add CHERI+RVFI_DII grant codes and copyrights

2020-07-06 17:39:25 +01:00

fpgautils

Avoid divide-by-zero in simulation model

2020-01-04 22:44:59 +00:00

procs

PC compression scheme for the instruction fetch pipeline.

2021-01-14 11:41:11 +00:00

LICENSE_RISCY-OOO

Initial load of files

2019-03-26 14:49:40 -04:00

Makefile

Revert "Fix whitespace in src_Core directory."

2020-03-23 14:40:02 +00:00