Added a toc to CHERI_CAP_API

This commit is contained in:
Alexandre Joannou
2022-09-30 17:30:04 +01:00
committed by GitHub
parent 11a88def9f
commit 6c71799edb

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@@ -1,3 +1,9 @@
:toc: macro
:toclevels: 4
:toc-title:
:toc-placement!:
:source-highlighter:
Given that HDL languages are not all as expressive as each other when it comes Given that HDL languages are not all as expressive as each other when it comes
to capturing an API, we express the CHERI CAP API in terms of pseudo-code, with to capturing an API, we express the CHERI CAP API in terms of pseudo-code, with
constructs that can at least map to Verilog, as well as higher level HDLs constructs that can at least map to Verilog, as well as higher level HDLs
@@ -21,6 +27,11 @@ A Verilog implementation can only capture this as a set of functions. We aim for
the higher level HDLs wrappers to make use of more advanced language features the higher level HDLs wrappers to make use of more advanced language features
where appropriate (structured types, typeclasses...). where appropriate (structured types, typeclasses...).
[discrete]
== Contents
toc::[]
=== CHERI CAP API "types" === CHERI CAP API "types"
==== Software permission bits ==== Software permission bits
@@ -487,8 +498,6 @@ function Tuple2#(Bool, Bit#(mem_sz)) toMem (t cap);
Note: Composing these two functions (in either order) is the identity. Note: Composing these two functions (in either order) is the identity.
=== Functions that can be cheap by relying on current capability representation
==== maskAddr ==== maskAddr
Mask the least significant bits of a CHERI capability address with a mask which Mask the least significant bits of a CHERI capability address with a mask which