Cheri-research/cheri-cap-lib
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Add SystemVerilog wrappers to generator

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This commit is contained in:
Ivan Ribeiro
2023-09-30 18:01:28 +01:00
parent 61e7b3e668
commit fd1f7c12a2
1 changed files with 30 additions and 0 deletions
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30
fusesoc/fusesoc-script.py
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@@ -67,6 +67,21 @@ vfiles = glob.glob(os.path.join(os.getcwd(), "*.v"))
print("verilog files:") print("verilog files:")
print(vfiles) print(vfiles)
# generate systemverilog files
subprocess.call(["python3", bsv_src_root + "/CHERICapWrap.py", "--generator", "sv"] + vfiles, cwd=workdir)
# collect systemverilog files and package files
pkgfiles = glob.glob(os.path.join(os.getcwd(), "*_pkg.sv"))
svfiles = glob.glob(os.path.join(os.getcwd(), "*.sv"))
#
# remove package files from systemverilog files
for pkgfile in pkgfiles:
svfiles.remove(pkgfile)
print("svfiles and pkgfiles:")
print(svfiles)
print(pkgfiles)
# write core file # write core file
with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as f: with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as f:
txt = 'CAPI=2:\n' txt = 'CAPI=2:\n'
@@ -74,12 +89,24 @@ with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as
txt += 'description: "Autogenerated Verilog & SystemVerilog versions of the cheri-cap-lib functions"\n\n' txt += 'description: "Autogenerated Verilog & SystemVerilog versions of the cheri-cap-lib functions"\n\n'
txt += 'filesets:\n' txt += 'filesets:\n'
txt += ' files_pkg:\n'
txt += ' files:\n'
txt += ' - '
txt += '\n - '.join([os.path.basename(file) for file in pkgfiles])
txt += '\n'
txt += ' file_type: systemVerilogSource\n'
txt += ' files_v:\n' txt += ' files_v:\n'
txt += ' files:\n' txt += ' files:\n'
txt += ' - ' txt += ' - '
txt += '\n - '.join([os.path.basename(file) for file in vfiles]) txt += '\n - '.join([os.path.basename(file) for file in vfiles])
txt += '\n' txt += '\n'
txt += ' file_type: verilogSource\n' txt += ' file_type: verilogSource\n'
txt += ' files_sv:\n'
txt += ' files:\n'
txt += ' - '
txt += '\n - '.join([os.path.basename(file) for file in svfiles])
txt += '\n'
txt += ' file_type: systemVerilogSource\n'
txt += '\n' txt += '\n'
txt += 'targets:\n' txt += 'targets:\n'
@@ -87,6 +114,9 @@ with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as
txt += ' description: "Default target that contains the Verilog files"\n' txt += ' description: "Default target that contains the Verilog files"\n'
txt += ' filesets:\n' txt += ' filesets:\n'
txt += ' - files_v\n' txt += ' - files_v\n'
txt += ' - files_pkg\n'
txt += ' - files_sv\n'
f.write(txt) f.write(txt)