16 lines
561 B
Core
16 lines
561 B
Core
CAPI=2:
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name: "ucam:cheri:cheri-cap-lib-verilog-generator"
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description: "Generates Verilog versions of the cheri-cap-lib functions"
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# the only parameter that this generator takes from the yaml file is
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# capwidth, which will be defined as a macro during bluespec compilation
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# the generated core file will have the name:
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# "ucam:cheri:cheri-cap-lib-verilog-autogen-$WIDTH"
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# where $WIDTH is the number after CAP in the capwidth parameter
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generators:
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cheri-cap-lib-gen:
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interpreter: python3
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command: fusesoc-script.py
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# TODO caching? for now, no
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