Add barebones fusesoc generator core

This adds a fusesoc generator to create the verilog files from the
bluespec source.

fusesoc/cheri-cap-lib-verilog-generator.core

@@ -0,0 +1,15 @@
+CAPI=2:
+name: "ucam:cheri:cheri-cap-lib-verilog-generator"
+description: "Generates Verilog versions of the cheri-cap-lib functions"
+
+# the only parameter that this generator takes from the yaml file is
+# capwidth,  which will be defined as a macro during bluespec compilation
+# the generated core file will have the name:
+# "ucam:cheri:cheri-cap-lib-verilog-autogen-$WIDTH"
+# where $WIDTH is the number after CAP in the capwidth parameter
+generators:
+  cheri-cap-lib-gen:
+    interpreter: python3
+    command: fusesoc-script.py
+    # TODO caching? for now, no
+

fusesoc/fusesoc-script.py

@@ -0,0 +1,92 @@
+import yaml
+import subprocess
+import argparse
+import shutil
+import os
+import glob
+
+# get yaml file location from single argument
+argparser = argparse.ArgumentParser()
+argparser.add_argument('yaml_file')
+
+args = argparser.parse_args()
+
+# load yaml file
+with open(args.yaml_file, "r") as yamlfile:
+  try:
+    print(yamlfile)
+    yamlcfg = yaml.safe_load(yamlfile)
+  except yaml.YAMLError as exc:
+    print(exc)
+
+
+# TODO debug
+print(yamlcfg)
+print(yamlcfg['parameters']['capwidth'])
+
+# use capwidth if provided, or default to CAP64
+cfgwidth = yamlcfg["parameters"]["capwidth"]
+capwidth = "CAP64" if cfgwidth in [None, ""] else cfgwidth
+
+# TODO debug
+print("capwidth:")
+print(capwidth)
+
+# get current working directory for file generation
+workdir = os.getcwd()
+
+# location of source files is actually one level above the location of the core file
+bsv_src_root = yamlcfg["files_root"] + "/.."
+
+# set up bluespec command + arguments
+bscargs = list()
+bscargs.extend(["bsc"])
+bscargs.extend(["-vdir", workdir])
+bscargs.extend(["-bdir", workdir])
+bscargs.extend(["-simdir", workdir])
+bscargs.extend(["-D", "{}".format(capwidth)])
+bscargs.extend(["-D", "RISCV"])
+bscargs.extend(["-verilog"])
+bscargs.extend(["-u"])
+bscargs.extend(["CHERICapWrap.bsv"])
+# TODO debug
+print(bscargs)
+
+# blocking call to bsc to generate verilog files
+subprocess.call(bscargs, cwd=bsv_src_root)
+
+
+
+
+print("CCL AUTOGEN NAME:")
+print("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]))
+
+
+# collect verilog files
+vfiles = glob.glob(os.path.join(os.getcwd(), "*.v"))
+print("verilog files:")
+print(vfiles)
+
+# write core file
+with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as f:
+  txt = 'CAPI=2:\n'
+  txt += 'name: "ucam:cheri:cheri-cap-lib-verilog-autogen-{}"\n'.format(capwidth[3:])
+  txt += 'description: "Autogenerated Verilog & SystemVerilog versions of the cheri-cap-lib functions"\n\n'
+
+  txt += 'filesets:\n'
+  txt += '  files_v:\n'
+  txt += '    files:\n'
+  txt += '      - '
+  txt += '\n      - '.join([os.path.basename(file) for file in vfiles])
+  txt += '\n'
+  txt += '    file_type: verilogSource\n'
+  txt += '\n'
+
+  txt += 'targets:\n'
+  txt += '  default:\n'
+  txt += '    description: "Default target that contains the Verilog files"\n'
+  txt += '    filesets:\n'
+  txt += '      - files_v\n'
+
+  f.write(txt)
+