65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:06:25 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap64_setKind O 115
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// wrap64_setKind_cap I 115
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// wrap64_setKind_kind I 7
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//
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// Combinational paths from inputs to outputs:
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// (wrap64_setKind_cap, wrap64_setKind_kind) -> wrap64_setKind
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap64_setKind(wrap64_setKind_cap,
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wrap64_setKind_kind,
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wrap64_setKind);
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// value method wrap64_setKind
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input [114 : 0] wrap64_setKind_cap;
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input [6 : 0] wrap64_setKind_kind;
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output [114 : 0] wrap64_setKind;
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// signals for module outputs
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wire [114 : 0] wrap64_setKind;
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// remaining internal signals
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reg [3 : 0] CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1;
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// value method wrap64_setKind
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assign wrap64_setKind =
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{ wrap64_setKind_cap[114:61],
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CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1,
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wrap64_setKind_cap[56:0] } ;
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// remaining internal signals
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always@(wrap64_setKind_kind)
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begin
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case (wrap64_setKind_kind[6:4])
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3'd0: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd15;
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3'd1: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd14;
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3'd2: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd13;
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3'd3: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd12;
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default: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 =
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wrap64_setKind_kind[3:0];
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endcase
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end
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endmodule // module_wrap64_setKind
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