93 lines
2.3 KiB
Python
93 lines
2.3 KiB
Python
import yaml
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import subprocess
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import argparse
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import shutil
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import os
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import glob
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# get yaml file location from single argument
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argparser = argparse.ArgumentParser()
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argparser.add_argument('yaml_file')
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args = argparser.parse_args()
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# load yaml file
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with open(args.yaml_file, "r") as yamlfile:
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try:
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print(yamlfile)
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yamlcfg = yaml.safe_load(yamlfile)
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except yaml.YAMLError as exc:
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print(exc)
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# TODO debug
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print(yamlcfg)
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print(yamlcfg['parameters']['capwidth'])
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# use capwidth if provided, or default to CAP64
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cfgwidth = yamlcfg["parameters"]["capwidth"]
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capwidth = "CAP64" if cfgwidth in [None, ""] else cfgwidth
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# TODO debug
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print("capwidth:")
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print(capwidth)
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# get current working directory for file generation
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workdir = os.getcwd()
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# location of source files is actually one level above the location of the core file
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bsv_src_root = yamlcfg["files_root"] + "/.."
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# set up bluespec command + arguments
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bscargs = list()
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bscargs.extend(["bsc"])
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bscargs.extend(["-vdir", workdir])
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bscargs.extend(["-bdir", workdir])
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bscargs.extend(["-simdir", workdir])
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bscargs.extend(["-D", "{}".format(capwidth)])
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bscargs.extend(["-D", "RISCV"])
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bscargs.extend(["-verilog"])
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bscargs.extend(["-u"])
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bscargs.extend(["CHERICapWrap.bsv"])
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# TODO debug
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print(bscargs)
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# blocking call to bsc to generate verilog files
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subprocess.call(bscargs, cwd=bsv_src_root)
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print("CCL AUTOGEN NAME:")
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print("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]))
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# collect verilog files
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vfiles = glob.glob(os.path.join(os.getcwd(), "*.v"))
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print("verilog files:")
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print(vfiles)
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# write core file
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with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as f:
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txt = 'CAPI=2:\n'
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txt += 'name: "ucam:cheri:cheri-cap-lib-verilog-autogen-{}"\n'.format(capwidth[3:])
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txt += 'description: "Autogenerated Verilog & SystemVerilog versions of the cheri-cap-lib functions"\n\n'
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txt += 'filesets:\n'
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txt += ' files_v:\n'
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txt += ' files:\n'
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txt += ' - '
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txt += '\n - '.join([os.path.basename(file) for file in vfiles])
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txt += '\n'
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txt += ' file_type: verilogSource\n'
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txt += '\n'
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txt += 'targets:\n'
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txt += ' default:\n'
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txt += ' description: "Default target that contains the Verilog files"\n'
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txt += ' filesets:\n'
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txt += ' - files_v\n'
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f.write(txt)
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