156 lines
5.9 KiB
Markdown
156 lines
5.9 KiB
Markdown
---
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title: "Challenging myself to understand RISC-V"
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summary: Basics of what is RISC-V
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date: 2021-05-30
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aliases: ["/riscv"]
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tags: ["RISCV","Open Source"]
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author: "Akilan Selvacoumar"
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draft: false
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aliases: [/technicalposts/riscv"]
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weight: 2
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---
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## Why do we need open standards for CPU Architecture ?
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- We want to allow users to see all the parts of the architecture
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without any proprietary constraints.
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- We want to have the rights to modify and distribute without paying any licensing fees and constraints in sharing.
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- With open standards it's easier to build on top of others work and possibly build CPU designs custom made for certain tasks.
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## What is RISC-V ?
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RISC-V is just an open source ISA (Instruction Set Architecture). An ISA is the software interface for the hardware. A single ISA can
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have many hardware implementations. In technical terms as ISA defines set of Instructions and how they behave such as:
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- Data types
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- Registers
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- Addressing modes
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- memory models
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- Protection levels
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- How is I/O are done
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- Virtual memory
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- Exceptions
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Another important factor to understand is that RISC-V is a standard
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and not an implementation. This means that the entire ISA is defined in a huge latex file which can be found on Github.
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Repo link: https://github.com/riscv/riscv-isa-manual
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The RISC-V is a well organized ISA and is divided into various categories and extensions in order to keep it as a modular design.
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The RISC-V is maintained the non profit organization called [RISC-V foundation](https://riscv.org/).
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### ["RISC-V in contrast was made specifically to be easy to teach while pragmatic enough to actually allow the implementation of high performance microprocessors."](https://medium.com/swlh/risc-v-assembly-for-beginners-387c6cd02c49)
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## Few companies working on RISC-V
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- [NVIDIA](https://riscv.org/wp-content/uploads/2017/05/Tue1345pm-NVIDIA-Sijstermans.pdf): using RISC-V in it's GPU
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- [SiFive](https://www.sifive.com/): Startup that allows you to create your own RISC-V board or use exsisting models they provide with great toolkits around them.
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- [Western Digital](https://blog.westerndigital.com/risc-v-swerv-core-open-source/): Focusing on building custom
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RISC-V cores.
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## Complier support for RISC-V ISA
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- [GCC](https://github.com/riscv/riscv-gnu-toolchain)
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- [LLVM/Clang](https://github.com/sifive/riscv-llvm)
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- [glibc](https://sourceware.org/git/?p=glibc.git)
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- [Go](https://github.com/riscvarchive/riscv-go)
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- [Rust](https://github.com/riscv-rust/riscv-rust-quickstart)
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## How is the RISC-V ISA organized
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In this section we look into how RISC-V is organised
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### RV N (Extension letter)
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- RV stands for RISC-V
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- N - Number of bits (Ex: 32 bits)
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- Extension letter: This is the Extension for the instruction
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sets (I stands for Integer)
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### Example Base ISA
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RV32I, RV64I, RV128I
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### Standard Extensions
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- M: Math
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- A: Atomic
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- F: Floating Point
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- D: Double Precision Floating Point
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#### - G: General Purpose (Includes, Integer, Math, Atomic, Floating Point and Double Precision Floating Point)
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### Linux supports
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#### RV64G
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This is called as RISC-V 64 bit General Purpose
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## Lets talk a bit indepth of RV32I
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RV32I is a base ISA and the easiest to understand.
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RV32I means it's RISC-V 32 bit Integer ISA.
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```
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Registers: x0-x31
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(x0 is hardwired to 0)
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```
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Each register is 32 bits which can be called as 1 word.
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Fig 1.0 [Simplified schematics of RV32I](https://github.com/Artoriuz/RV32I-SC)
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Now we will recall the basics and try to understand
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how to read an instruction.
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```
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add rd,rs1,rs2
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```
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- add: is the opcode
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- rd: is the destination register
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- rs1: Source register 1
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- rs2: Source register 2
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Fig 1.1 [Assembly instructions for RV32I](https://github.com/jameslzhu/riscv-card/blob/master/riscv-card.pdf)
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Fig 1.2 [Registers for RV32I](https://github.com/jameslzhu/riscv-card/blob/master/riscv-card.pdf)
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## Interesting research papers
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- [Implementing RISC-V System-on-Chip for Acceleration of Convolution Operation and Activation Function Based on FPGA (Field programmable gate arrays)](https://ieeexplore.ieee.org/document/8564810): FGPA are mostly for application specific integrated circuits. An example would be Intel using FGPA to
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prototype new chips. The objective of the paper was to design
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a RISC-V processor for specific tasks such as Convolution functions and activation functions. The result was that the
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RISC-V processor was faster than CPU + co-processor mode and
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used lesser than the CPU + GPU mode.
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- [Towards deep learning using Tensorflow lite on RISC-V](
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https://edge.seas.harvard.edu/files/edge/files/carrv_workshop_submission_2019_camera_ready.pdf
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): This paper focuses on ISA extensions customized for
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machine learning kernels. The software infrastructure implemented was optimized for neural network execution.
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The following was integrated into Tensorflow lite. The
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result was that instructions was reduced by 8X.
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- [A compiler comparison in the RISC-V ecosystem](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9191411): Comparing LLVM and GCC performance on RISC-V. LLVM and GCC
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produce same binary size but both have different execution
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times.
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## Interesting Open Source projects
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- [RISCBoy](https://github.com/Wren6991/RISCBoy): It is an open-source portable games console, designed from scratch.
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RISC-V compatible CPU. Has raster graphics pipelines and display controllers. It consists of other infrastructure such as memory
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controllers and GPIO ports. It also consists of a CAD design of
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the PCB layout.
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- [Potato](https://github.com/skordal/potato): The Potato Processor is a simple RISC-V processor written in VHDL for use in FPGAs. It implements the 32-bit integer subset of the RISC-V Specification version 2.0.
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- [Vulcan](https://github.com/vmmc2/Vulcan): RISC-V instruction set simulation built for education using flutter.
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