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added changes to paper FAT pointer section

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Akilan Selvacoumar
2025-04-10 12:05:25 +01:00
parent 8cf048b6b2
commit 3c615fe015
7 changed files with 52 additions and 42 deletions
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and the use of huge pages. Concurrently, advancements in hardware-level system security—exemplified by the Capability Hardware
Enhanced RISC Instructions (CHERI) architecture—offer additional opportunities for improving TLB performance. CHERI introduces
capability-based addressing, a novel approach that enhances system security by associating capabilities with memory pointers. By leveraging capability-based
addressing, memory allocators can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that
addressing, we introduce a memory allocator that can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that
our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications.
\end{abstract}
@@ -342,13 +342,13 @@ workloads that rely heavily on large datasets.
Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
~\cite{woodruff_cheri_2014} architecture, present additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
operations. By integrating CHERI’s compressed~\cite{woodruff_cheri_2019} encoded bounds with the use of huge pages, We have shown it is possible to track and manage
operations. By integrating CHERI’s compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages, We have shown it is possible to track and manage
large, physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces TLB pressure by minimising the number of
entries required to map extensive memory regions, thereby decreasing TLB misses and improving address translation performance.
Furthermore, it accelerates memory-intensive tasks by reducing the overhead associated with managing fragmented or non-contiguous
Furthermore, it accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous
memory allocations. The contributions for the following paper are as follows:
\begin{itemize}
\item \textbf{Fat pointer Based Range Addresses}: Introduces fat-pointers that include memory bounds, allowing
\item \textbf{Fat Addresses Translations}: Introduces fat-pointers that include memory bounds, allowing
efficient tracking and management of physically contiguous memory regions (section ~\ref{sec:FatPointerTranslations}).
\item \textbf{CHERI’s Capability-based Optimization}: Demonstrates how CHERI's architecture can be
@@ -454,15 +454,21 @@ and abstraction extensions for scalable software compartmentalization.
\section{Fat Address Translations}
\label{sec:FatPointerTranslations}
Fat-pointer Address Translations, combined with the capabilities of the CHERI (Capability Hardware Enhanced RISC Instructions)
architecture, introduce robust memory safety and security features by incorporating additional metadata
with memory pointers. Fat-pointer Address Translations enhanced architecture utilizes concepts such as FlexPointer~\cite{chen_flexpointer_2023},
Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to manage memory effectively.
This section talks about how Fat-pointer Address Translations uses the CHERI architecture to
bring about block based allocations in physically contiguous memory. Fat-pointer Address Translations
leverages techniques like FlexPointer~\cite{chen_flexpointer_2023} and Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to
achieve lesser pressure in the TLB. A key component
in this implementation is the use of range addresses with CHERI CC~\cite{woodruff_cheri_2019}.
Range addresses play a pivotal role within the Fat Address Translations implementation, defining memory
regions bounded by a starting address (Upper) and an ending address (Lower).
These range addresses are encoded within FAT-pointers, allowing for precise
control using CHERI CC~\cite{woodruff_cheri_2019} bounds over memory regions to reduce the number of TLB operations needed.
% Fat-pointer Address Translations, combined with the capabilities of the CHERI
% architecture, introduce robust memory safety and security features by incorporating additional metadata
% with memory pointers. Fat-pointer Address Translations enhanced architecture uses concepts such as FlexPointer~\cite{chen_flexpointer_2023},
% Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to manage memory effectively.
% Range addresses play a pivotal role within the Fat Address Translations implementation, defining memory
% regions bounded by a starting address (Upper) and an ending address (Lower).
% These range addresses are encoded within FAT-pointers, allowing for precise
% control using CHERI CC~\cite{woodruff_cheri_2019} bounds over memory regions to reduce the number of TLB operations needed.
% The functionality of ranges encompasses several key aspects:
% \begin{itemize}
@@ -486,6 +492,14 @@ control using CHERI CC~\cite{woodruff_cheri_2019} bounds over memory regions to
% \end{minipage}
\end{figure*}
Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (malloc()) and a proposed Fat-pointer Address
Translation method. The standard approach involves a C program interacting with a custom allocator, utilizing 48-bit
free virtual addresses and a TLB walk (L1, L2, L3) to achieve non-contiguous allocation in physical memory.
This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks.
In contrast, the Fat-pointer Address Translations method employs a custom allocator leveraging
physically contiguous memory by using CHERI to encode
bounds within the pointers and as show in the figure \ref{fig:HighOverviewArchitecture} there is almost no reliance on walking the TLB.
Figure \ref{fig:HighOverviewArchitecture} illustrates
the methodology employed to use the CHERI
128-bit FAT-pointer scheme for facilitating