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Akilan Selvacoumar
2025-04-10 20:20:13 +01:00
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45
docs/EuroSys/Paper/paper.aux
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@@ -79,13 +86,6 @@
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@@ -498,22 +498,23 @@ free virtual addresses and a TLB walk (L1, L2, L3) to achieve non-contiguous all
This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks.
In contrast, the Fat-pointer Address Translations method employs a custom allocator leveraging
physically contiguous memory by using CHERI to encode
bounds within the pointers and as show in the figure \ref{fig:HighOverviewArchitecture} there is almost no reliance on walking the TLB.
bounds within the pointers and as show in the figure \ref{fig:HighOverviewArchitecture} there is almost no reliance on walking the TLB hierarchy.
Figure \ref{fig:HighOverviewArchitecture} illustrates
the methodology employed to use the CHERI
128-bit FAT-pointer scheme for facilitating
block-based memory management on physically
contiguous memory,which is depicted on the
right side of the figure.
This technique contrasts with the
conventional approach.
% Figure \ref{fig:HighOverviewArchitecture} illustrates
% the methodology employed to use the CHERI
% 128-bit FAT-pointer scheme for facilitating
% block-based memory management on physically
% contiguous memory,which is depicted on the
% right side of the figure.
% This technique contrasts with the
% conventional approach.
We explore how using huge pages
with CHERI bounds can reduce the
number of TLB entries required.
% We explore how using huge pages
% with CHERI bounds can reduce the
% number of TLB entries required.
\subsection{Encoding Ranges as Bounds to the Pointer}
\label{sec:RangeMemory}
\begin{figure}[h]
\includegraphics[width=0.4\textwidth]{diagram/AllocationOverview24.png}
\caption{Range of memory}
@@ -522,9 +523,12 @@ number of TLB entries required.
% Integrating range bounds directly into FAT-pointers enables the CHERI architecture
% to enforce memory access restrictions at the pointer level thus allowing
% tracking of memory ranges on a pointer level.
In this implementation, memory ranges are established using
bounds encoded within the FAT-pointer, adhering to the CHERI
CHERI 128-bit bounds compression scheme~\cite{woodruff_cheri_2019}.
A memory range in FAT has 2 points to track memory in physical contiguous space which
is the top and bottom. These 2 points are 2 virtual addresses and the range consists of
addresses which lie within this and constitutes as addresses allocated by invoking malloc.
In FAT memory ranges are established using
bounds encoded within the pointer, adhering to CHERI CC~\cite{woodruff_cheri_2019}
as referred in section ~\ref{sec:128bitCompressedBounds}.
Figure \ref{fig:RangeOfMemory} illustrates a straightforward use-case in which the dark pink line represents a single,
large contiguous memory area, or huge page. Within this huge page, the orange and blue lines indicate
@@ -551,20 +555,26 @@ By using the CHERI bounds, this method maintains the contiguity of the allocated
% within the FAT-Pointer which can be repurposed as ranges in memory allocators with custom allocation
% sizes rather than fixed sized TLB entries.
We use CHERI CC~\cite{woodruff_cheri_2019} (Compressed Capabilities) to track regions of memory in physically contiguous space.
We use CHERI CC~\cite{woodruff_cheri_2019} to track regions of memory in physically contiguous space.
CHERI CC consists of compressed bounds that represent a 128-bit pointer within a 64-bit virtual address
system. Our approach utilizes a single-cycle encoding and decoding mechanism for efficiency. While CHERI
CC was originally designed for memory protection, it can also be repurposed for tracking memory regions,
eliminating the need for multiple TLB entries for each allocation.
system. Our approach uses the work of CHERI CC by using a single cycle t0 decode bounds from the
capability register and the bounds which are decoded are repurposed for tracking memory regions.
% Our approach utilizes a single-cycle encoding and decoding mechanism for efficiency. While CHERI
% CC was originally designed for memory protection, it can also be repurposed for tracking memory regions,
% eliminating the need for multiple TLB entries for each allocation.
One key analysis of CHERI CC highlights that allocators like Jemalloc typically allocate objects under
512 bytes. When an object’s bounds cannot be precisely represented, padding is required to ensure
memory safety. However, it has been observed that Jemalloc rarely needs more than 6 bits~\cite{woodruff_cheri_2019} to store the
exponent values within compressed bounds.
Allocators like Jemalloc typically allocate objects under
512 bytes~\cite{woodruff_cheri_2019}. When an object’s bounds cannot be precisely represented, padding is required to ensure
memory safety. However, it has been observed that Jemalloc rarely needs more than 6 bits to store the
exponent values within compressed bounds. This means that the default behavior of allocators such as Jemalloc, would allow precise
representation of bounds within CHERI CC.
This means that the default behavior of allocators such as Jemalloc, would allow precise
representation of bounds within CHERI CC. With our implementation rather than using
fixed size TLB entries we use the CHERI CC bounds to be repurposed to encode dynamic sized addresses ranges.
With FAT rather than using fixed size TLB entries page sizes (such as 4KB, 2MB and 1GB pages).
We use CHERI CC bounds to be dynamic in size to be defined based on the size provided when calling
malloc. Offering a more flexible alternative than fixed-size TLB entries.
% We use the CHERI CC
% bounds to be repurposed to encode dynamic sized addresses ranges.
% These pointers can then be repurposed as memory ranges
% in custom memory allocators, offering a more flexible alternative to fixed-size TLB entries.
@@ -581,6 +591,13 @@ fixed size TLB entries we use the CHERI CC bounds to be repurposed to encode dyn
\caption{Fat-pointer Address Translations using huge pages}
\label{fig:HugePages}
\end{figure}
To build up based on Section ~\ref{sec:RangeMemory} and ~\ref{sec:128bitCompressedBounds}
we are able to pre-allocate memory using Huge pages and are able to mark smaller allocations
using ranges by storing them as bounds within the pointer. Each of the memory ranges can be
called a block. Since we have numerous blocks inside a huge page we allow block based
memory patters within physically contiguous memory. As demonstrated with the allocator
implementation in section ~\ref{sec:MemoryAllocator}.
Traditional address translation methods rely on hierarchical
structures to map virtual addresses to physical addresses.
This often requires multiple entries to handle different
@@ -857,11 +874,22 @@ for use with huge pages, demonstrates a clear advantage in scenarios where memor
patterns benefit from its design. The results align with expectations, showcasing the impact
of its capability to handle memory more efficiently by leveraging huge pages.
<points metric based>
- Each benchmark reflection for the metric
- summary based on each benchmark reflected
\begin{itemize}
\item L1 DTLB reads: There was noticeable reduction of L1 DTLB reads for kmeans of about on average
4\% lesser and for Glibc there was significant reduction of 50\% than Jemalloc.
\item L2 DTLB reads: For all the benchmarks on figure \ref{fig:bargraph} there was on average 98\%
reduction on L2 DTLB reads. Which demonstrates that all TLB translations are read at the L1 TLB
cache.
- summarize all the bullet points.
\item L1 DTLB walks: Due to most of the TLB entries getting hit at the L1TLB there is no need
to walk the TLB cache hierarchy. This is shown by on average 99\% reduction in DTLB walks.
\item L1 DTLB refills: Since there are lesser DTLB walks and most reads are done at the L1 DTLB
layer there is no need for numerous TLB refills to take place. Our benchmarks show on average
a 99\% reduction on DTLB refills.
\end{itemize}
A particularly striking observation is the significant reduction in data TLB walks,
L2 data TLB reads, and TLB refills—consistently showing a 90\% decrease across all