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fixed eurosys Robs changes

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Akilan Selvacoumar
2025-04-25 15:00:38 +01:00
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8 changed files with 476 additions and 380 deletions
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55
docs/EuroSys/Paper/paper.aux
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132
docs/EuroSys/Paper/paper.bbl
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@@ -1,80 +1,141 @@
\begin{thebibliography}{10}
\begin{thebibliography}{19}
\providecommand{\natexlab}[1]{#1}
\providecommand{\url}[1]{\texttt{#1}}
\expandafter\ifx\csname urlstyle\endcsname\relax
\providecommand{\doi}[1]{doi: #1}\else
\providecommand{\doi}{doi: \begingroup \urlstyle{rm}\Url}\fi
\bibitem{mittal_survey_2017}
\bibitem[Mittal()]{mittal_survey_2017}
Sparsh Mittal.
\newblock A survey of techniques for architecting {TLBs}.
\newblock 29(10):e4061.
\newblock 29\penalty0 (10):\penalty0 e4061.
\newblock ISSN 1532-0634.
\newblock \doi{10.1002/cpe.4061}.
\newblock URL \url{https://onlinelibrary.wiley.com/doi/abs/10.1002/cpe.4061}.
\newblock \_eprint: https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.4061.
\bibitem{panwar_hawkeye_2019}
\bibitem[Panwar et~al.()Panwar, Bansal, and Gopinath]{panwar_hawkeye_2019}
Ashish Panwar, Sorav Bansal, and K.~Gopinath.
\newblock {HawkEye}: Efficient fine-grained {OS} support for huge pages.
\newblock In {\em Proceedings of the Twenty-Fourth International Conference on
\newblock In \emph{Proceedings of the Twenty-Fourth International Conference on
Architectural Support for Programming Languages and Operating Systems}, pages
347--360. {ACM}.
\newblock ISBN 978-1-4503-6240-5.
\newblock \doi{10.1145/3297858.3304064}.
\newblock URL \url{https://dl.acm.org/doi/10.1145/3297858.3304064}.
\bibitem{woodruff_cheri_2014}
\bibitem[Woodruff et~al.({\natexlab{a}})Woodruff, Watson, Chisnall, Moore,
Anderson, Davis, Laurie, Neumann, Norton, and Roe]{woodruff_cheri_2014}
Jonathan Woodruff, Robert~N.M. Watson, David Chisnall, Simon~W. Moore, Jonathan
Anderson, Brooks Davis, Ben Laurie, Peter~G. Neumann, Robert Norton, and
Michael Roe.
\newblock The {CHERI} capability model: revisiting {RISC} in an age of risk.
\newblock 42(3):457--468.
\newblock 42\penalty0 (3):\penalty0 457--468, {\natexlab{a}}.
\newblock ISSN 0163-5964.
\newblock \doi{10.1145/2678373.2665740}.
\newblock URL \url{https://doi.org/10.1145/2678373.2665740}.
\bibitem{woodruff_cheri_2019}
\bibitem[Woodruff et~al.({\natexlab{b}})Woodruff, Joannou, Xia, Fox, Norton,
Chisnall, Davis, Gudka, Filardo, Markettos, Roe, Neumann, Watson, and
Moore]{woodruff_cheri_2019}
Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert~M.
Norton, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel~W. Filardo,
A.~Theodore Markettos, Michael Roe, Peter~G. Neumann, Robert N.~M. Watson,
and Simon~W. Moore.
\newblock {CHERI} concentrate: Practical compressed capabilities.
\newblock 68(10):1455--1469.
\newblock 68\penalty0 (10):\penalty0 1455--1469, {\natexlab{b}}.
\newblock ISSN 0018-9340, 1557-9956, 2326-3814.
\newblock \doi{10.1109/TC.2019.2914037}.
\newblock URL \url{https://ieeexplore.ieee.org/document/8703061/}.
\bibitem{TLBReach}
\bibitem[Pham et~al.(2014)Pham, Bhattacharjee, Eckert, and Loh]{TLBReach}
Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, and Gabriel~H. Loh.
\newblock Increasing tlb reach by exploiting clustering in page translations.
\newblock In {\em 2014 IEEE 20th International Symposium on High Performance
\newblock In \emph{2014 IEEE 20th International Symposium on High Performance
Computer Architecture (HPCA)}, pages 558--567, 2014.
\newblock \doi{10.1109/HPCA.2014.6835964}.
\bibitem{THP}
Juan Navarro.
\bibitem[Navarro et~al.(2003)Navarro, Iyer, Druschel, and Cox]{THP}
Juan Navarro, Sitararn Iyer, Peter Druschel, and Alan Cox.
\newblock Practical, transparent operating system support for superpages.
\newblock \emph{SIGOPS Oper. Syst. Rev.}, 36\penalty0 (SI):\penalty0 89–104,
December 2003.
\newblock ISSN 0163-5980.
\newblock \doi{10.1145/844128.844138}.
\newblock URL \url{https://doi.org/10.1145/844128.844138}.
\bibitem{Shadow_superpages}
\bibitem[Cornea et~al.(2003)Cornea, Harrison, and Tang]{IntelItanium}
Marius Cornea, John Harrison, and Ping Tak~Peter Tang.
\newblock Intel® itanium® floating-point architecture.
\newblock In \emph{Proceedings of the 2003 Workshop on Computer Architecture
Education: Held in Conjunction with the 30th International Symposium on
Computer Architecture}, WCAE '03, page 3–es, New York, NY, USA, 2003.
Association for Computing Machinery.
\newblock ISBN 9781450347327.
\newblock \doi{10.1145/1275521.1275526}.
\newblock URL \url{https://doi.org/10.1145/1275521.1275526}.
\bibitem[Park and Park(2001)]{Shadow_superpages}
Cheol~Ho Park and Daeyeon Park.
\newblock Aggressive superpage support with the shadow memory and the
partial-subblock tlb.
\newblock {\em Microprocessors and Microsystems}, 25(7):329--342, 2001.
\newblock \emph{Microprocessors and Microsystems}, 25\penalty0 (7):\penalty0
329--342, 2001.
\newblock ISSN 0141-9331.
\newblock \doi{https://doi.org/10.1016/S0141-9331(01)00125-9}.
\newblock URL
\url{https://www.sciencedirect.com/science/article/pii/S0141933101001259}.
\bibitem{DirectSegment}
\bibitem[Basu et~al.(2013)Basu, Gandhi, Chang, Hill, and Swift]{DirectSegment}
Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark~D. Hill, and Michael~M.
Swift.
\newblock Efficient virtual memory for big memory servers.
\newblock {\em SIGARCH Comput. Archit. News}, 41(3):237–248, June 2013.
\newblock \emph{SIGARCH Comput. Archit. News}, 41\penalty0 (3):\penalty0
237–248, June 2013.
\newblock ISSN 0163-5964.
\newblock \doi{10.1145/2508148.2485943}.
\newblock URL \url{https://doi.org/10.1145/2508148.2485943}.
\bibitem{karakostas_redundant_2015}
\bibitem[Karakostas et~al.()Karakostas, Gandhi, Ayar, Cristal, Hill,
{McKinley}, Nemirovsky, Swift, and Ünsal]{karakostas_redundant_2015}
Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrián Cristal, Mark~D.
Hill, Kathryn~S. {McKinley}, Mario Nemirovsky, Michael~M. Swift, and Osman
Ünsal.
\newblock Redundant memory mappings for fast access to large memories.
\newblock In {\em Proceedings of the 42nd Annual International Symposium on
\newblock In \emph{Proceedings of the 42nd Annual International Symposium on
Computer Architecture}, pages 66--78. {ACM}.
\newblock ISBN 978-1-4503-3402-0.
\newblock \doi{10.1145/2749469.2749471}.
\newblock URL \url{https://dl.acm.org/doi/10.1145/2749469.2749471}.
\bibitem{chen_flexpointer_2023}
\bibitem[Chen et~al.(2023)Chen, Tong, Yang, Yi, and
Cheng]{chen_flexpointer_2023}
Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, and Xu~Cheng.
\newblock {FlexPointer}: Fast address translation based on range {TLB} and
tagged pointers.
\newblock 20(2):1--24.
\newblock Flexpointer: Fast address translation based on range tlb and tagged
pointers.
\newblock \emph{ACM Trans. Archit. Code Optim.}, 20\penalty0 (2), March 2023.
\newblock ISSN 1544-3566.
\newblock \doi{10.1145/3579854}.
\newblock URL \url{https://doi.org/10.1145/3579854}.
\bibitem{jemalloc}
{JEMALLOC}.
\bibitem[Evans(2006)]{jemalloc}
Jason Evans.
\newblock A scalable concurrent malloc (3) implementation for freebsd.
\newblock In \emph{Proc. of the bsdcan conference, ottawa, canada}, 2006.
\bibitem{cheribsd}
\bibitem[che()]{cheribsd}
Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial.
\newblock URL
\url{https://www.cheribsd.org/tutorial/23.11/benchmark/index.html}.
\bibitem{Morello}
\bibitem[Mor()]{Morello}
Department of computer science and technology – {CHERI}: The arm morello
board.
\newblock URL
\url{https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-morello.html}.
\bibitem{BenchmarkABI}
\bibitem[Watson et~al.(2023)Watson, Clarke, Sewell, Woodruff, Moore, Barnes,
Grisenthwaite, Stacer, Baranga, and Richardson]{BenchmarkABI}
Robert N.~M. Watson, Jessica Clarke, Peter Sewell, Jonathan Woodruff, Simon~W.
Moore, Graeme Barnes, Richard Grisenthwaite, Kathryn Stacer, Silviu Baranga,
and Alexander Richardson.
@@ -84,23 +145,26 @@ Robert N.~M. Watson, Jessica Clarke, Peter Sewell, Jonathan Woodruff, Simon~W.
Laboratory, 15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom, phone
+44 1223 763500, September 2023.
\bibitem{PerformanceCounter}
\bibitem[Per()]{PerformanceCounter}
Arm architecture reference manual for a-profile architecture.
\newblock URL \url{https://developer.arm.com/documentation/ddi0487/latest}.
\bibitem{Benchmark}
\bibitem[Ben()]{Benchmark}
{CHERI}-allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at
main · akilan1999/{CHERI}-allocator.
\newblock URL
\url{https://github.com/Akilan1999/CHERI-Allocator/blob/main/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c}.
\bibitem{singh1993}
\bibitem[Singh(1993)]{singh1993}
Jaswinder~Pal Singh.
\newblock {\em Parallel Hierarchical N-body Methods and Their Implications for
\newblock \emph{Parallel Hierarchical N-body Methods and Their Implications for
Multiprocessors}.
\newblock PhD thesis, Stanford University, February 1993.
\bibitem{holt1995}
\bibitem[Holt and Singh(1995)]{holt1995}
C.~Holt and Jaswinder~Pal Singh.
\newblock Hierarchical n-body methods on shared address space multiprocessors.
\newblock In {\em SIAM Conference on Parallel Processing for Scientific
\newblock In \emph{SIAM Conference on Parallel Processing for Scientific
Computing}, February 1995.
\newblock To appear.

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@@ -54,6 +54,7 @@
\usepackage{lipsum}
\usepackage{stfloats}
\usepackage{grffile}
\usepackage{hyperref}
\lstset{basicstyle=\small\ttfamily,columns=fullflexible}
@@ -350,7 +351,7 @@ workloads that rely heavily on large datasets.
Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
~\cite{woodruff_cheri_2014} architecture presents additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
operations. By integrating CHERI's compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages, We have shown it is possible to track, manage
operations. By integrating CHERI's compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages we have shown it is possible to track, manage
large and physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces the TLB pressure by minimising the number of
entries required to map extensive memory regions thereby decreasing TLB misses and improving address translation performance.
Furthermore, we introduce FAT which accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous
@@ -392,7 +393,7 @@ The x86-64 architecture supports huge pages of 2 MB and 1 GB which are backed by
% Alternate segment technique
% - JayneelGandhi,ArkapravaBasu,MarkD.Hill,andMichaelM.Swift.2014.Efficientmemoryvirtualization:Reducing
For instance, allocating 1 MB with 4 KB base pages requires 256 PTEs (Page Table Entries) and in contrast using a 2 MB huge page would waste
half of the memory space. Some architectures offer more page size choices, such as Intel Itanium which
half of the memory space. Some architectures offer more page size choices, such as Intel Itanium~\cite{IntelItanium} which
allows different areas of the address space to have their own page sizes. Itanium uses a hash page table to organise huge
pages and without significant changes to the conventional page table. It only helps reduce page walk overheads.
Huge page tunable base page size permits the OS to adjust the base page, but still faces internal fragmentation problems
@@ -468,7 +469,7 @@ provided to support fine-grained memory protection (including spatial, referenti
for scalable software compartmentalisation.
\subsection{CHERI CC}
CHERI Concentrate: Practical Compressed Capabilities\cite{woodruff_cheri_2019} introduces a compression scheme for CHERI that aims to address the performance and compatibility challenges associated with
CHERI CC(Concentrate Compressed Capabilities)~\cite{woodruff_cheri_2019} introduces a compression scheme for CHERI that aims to address the performance and compatibility challenges associated with
capability pointers. Capability pointers enhance memory safety by embedding bounds and permissions directly
within pointers. Traditional implementations of CHERI double their size leading in bounds to increased memory usage. CHERI CC
proposes a compression strategy that preserves security while reducing size and inefficiencies. Key contributions include a floating-point
@@ -476,7 +477,7 @@ bound encoding technique with an internal exponent mechanism that offers greater
\section{Fat Address Translations}
\label{sec:FatPointerTranslations}
Fat Address Translations (FAT) uses the CHERI architecture to
Fat Address Translations (FAT) is our new memory allocator for CHERI. It uses the CHERI architecture to
bring about block-based allocations in physically contiguous memory.
FAT leverages techniques like FlexPointer~\cite{chen_flexpointer_2023} and RMM~\cite{karakostas_redundant_2015} to
reduce pressure on the TLB. A key component
@@ -514,7 +515,7 @@ in this implementation is the use of range addresses with CHERI CC~\cite{woodruf
% \end{minipage}
\end{figure*}
Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (\textit{malloc()}) and the proposed FAT method. The standard approach involves a C program interacting with a custom allocator which uses 48-bit
Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (\textit{malloc}) and the proposed FAT method. The standard approach involves a C program interacting with a custom allocator which uses 48-bit
virtual addresses and a TLB walker (L1, L2 and L3 cache) to achieve non-contiguous allocation in physical memory.
This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks.
In contrast, the FAT method employs a custom allocator leveraging
@@ -742,7 +743,7 @@ which is a mechanism supported by modern architectures to optimise memory manage
allocating a fixed block of 1 GB physically contiguous memory. This decision is driven by the
architectural constraints of contemporary systems, particularly ARM-based CPUs. Where 1 GB represents
the largest supported page size. By leveraging huge pages, the algorithm reduces the overhead associated
with page table management and enhances memory access. which is critical for performance-sensitive
with page table management and enhances memory access which is critical for performance-sensitive
applications and kernel-level operations.
\section{Evaluation}
@@ -912,7 +913,7 @@ This extension is described by Holt and Singh ~\cite{holt1995}.
\caption{\label{fig:bargraph}Percentage difference between the modified memory allocator against the default system memory allocator}
\end{figure*}
The graph (Figure \ref{fig:bargraph}) highlights the performance comparison between the modified memory allocator and
Figure \ref{fig:bargraph} highlights the performance comparison between the modified memory allocator and
Jemalloc, the default memory allocator. The FAT memory allocator is specifically optimised
for use with huge pages and demonstrates a clear advantage in scenarios where memory allocation
patterns benefit from its design. The results align with expectations, showcasing the impact
@@ -920,7 +921,7 @@ of its capability to handle memory more efficiently by leveraging huge pages.
\begin{itemize}
\item L1 DTLB reads: There was a noticeable reduction of L1 DTLB reads for kmeans of about an average of
4\% lesser and for Glibc there was significant reduction of 50\% less than Jemalloc.
4\% less than Jemalloc and for Glibc there was significant reduction of 50\% less than Jemalloc.
\item L2 DTLB reads: For all the benchmarks on figure \ref{fig:bargraph} there was on average 98\%
reduction in L2 DTLB reads. This demonstrates that all the TLB translations are read at the L1 TLB
@@ -943,11 +944,11 @@ to be resolved directly at the L1 TLB, the need to walk through the deeper TLB h
largely eliminated. This reduction in translation overhead is a key factor in the allocators
performance for certain types of workloads.
The microbenchmarks which are crafted to emphasise memory read operations, highlight the
The micro benchmarks which are crafted to emphasise memory read operations, highlight the
allocators strengths. These tests simulate frequent and intensive memory access patterns,
where the reduction in TLB misses directly translate into measurable performance gains.
On average, the FAT allocator achieves a 50\% reduction in wall clock runtimes for
these workloads. Underscoring its ability to optimise high-throughput memory operations.
these workloads underscoring its ability to optimise high-throughput memory operations.
On the other hand, macro benchmarks which represent larger and more complex real-world applications,
exhibit minimal differences in wall clock runtimes when using the FAT allocator.
@@ -1006,8 +1007,7 @@ insights into the allocators interaction with system-level caching and memory tr
While the allocator excels in scenarios emphasising on high-memory throughput. Its impact on
macro benchmarks is less pronounced. This suggests that its benefits are most relevant for
applications with frequent and intensive memory operations rather than those constrained by
computation or I/O bottlenecks.
applications with frequent and intensive memory operations rather than are compute-bound workloads.
% \section{Future work}
% The current experimental setup on the ARM Morello board is constrained by the requirement that all memory reads must
@@ -1032,7 +1032,7 @@ computation or I/O bottlenecks.
\section{Conclusion} %Title of the Conclusion
This paper addresses the growing disparity between application workloads and the capacity of TLBs.
To mitigate this gap, we proposed leveraging physically contiguous memory with CHERI bounds to reduce TLB walks.
To mitigate this gap, FAT proposed leveraging physically contiguous memory with CHERI bounds to reduce TLB walks.
We designed a memory allocator that uses huge pages with the CHERI CC scheme to track allocations within the
allocated huge page. This approach reduces the number of TLB entries needed while using bounds
to minimise fragmentation.
@@ -1587,7 +1587,7 @@ by repurposing CHERI's capability-based model with the use of huge pages.
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% massa et mattis lacinia.
\bibliographystyle{unsrt}
\bibliographystyle{unsrtnat}
\bibliography{paperReferences}
\end{document}

95
docs/EuroSys/Paper/paperReferences.bib
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@@ -14,13 +14,25 @@ abstract = {While superpages are an efficient solution to increase TLB reach, st
}
@article{THP,
title = {Practical, transparent operating system support for superpages},
abstract = {Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer ({TLB}) to map a large physical memory region into a virtual address space. This dramatically increases {TLB} coverage, reduces {TLB} misses, and promises performance improvements for many applications. However, supporting superpages poses several challenges to the operating system, in terms of superpage allocation and promotion tradeoffs, fragmentation control, etc. We analyze these issues, and propose the design of an effective superpage management system. We implement it in {FreeBSD} on the Alpha {CPU}, and evaluate it on real workloads and benchmarks. We obtain substantial performance benefits, often exceeding 30\%; these benefits are sustained even under stressful workload scenarios.},
author = {Navarro, Juan},
langid = {english},
file = {Navarro - Practical, transparent operating system support fo.pdf:/Users/akilan/Zotero/storage/R9MSCWQX/Navarro - Practical, transparent operating system support fo.pdf:application/pdf},
author = {Navarro, Juan and Iyer, Sitararn and Druschel, Peter and Cox, Alan},
title = {Practical, transparent operating system support for superpages},
year = {2003},
issue_date = {Winter 2002},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {36},
number = {SI},
issn = {0163-5980},
url = {https://doi.org/10.1145/844128.844138},
doi = {10.1145/844128.844138},
abstract = {Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer (TLB) to map a large physical memory region into a virtual address space. This dramatically increases TLB coverage, reduces TLB misses, and promises performance improvements for many applications. However, supporting superpages poses several challenges to the operating system, in terms of superpage allocation and promotion tradeoffs, fragmentation control, etc. We analyze these issues, and propose the design of an effective superpage management system. We implement it in FreeBSD on the Alpha CPU, and evaluate it on real workloads and benchmarks. We obtain substantial performance benefits, often exceeding 30\%; these benefits are sustained even under stressful workload scenarios.},
journal = {SIGOPS Oper. Syst. Rev.},
month = dec,
pages = {89–104},
numpages = {16}
}
@INPROCEEDINGS{TLBReach,
author={Pham, Binh and Bhattacharjee, Abhishek and Eckert, Yasuko and Loh, Gabriel H.},
booktitle={2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)},
@@ -99,23 +111,23 @@ keywords = {tanslation lookaside buffer, virtual memory}
}
@article{chen_flexpointer_2023,
title = {{FlexPointer}: Fast Address Translation Based on Range {TLB} and Tagged Pointers},
volume = {20},
issn = {1544-3566, 1544-3973},
url = {https://dl.acm.org/doi/10.1145/3579854},
doi = {10.1145/3579854},
shorttitle = {{FlexPointer}},
abstract = {Page-based virtual memory relies on {TLBs} to accelerate the address translation. Nowadays, the gap between application workloads and the capacity of {TLB} continues to grow, bringing many costly {TLB} misses and making the {TLB} a performance bottleneck. Previous studies seek to narrow the gap by exploiting the contiguity of physical pages. One promising solution is to group pages that are both virtually and physically contiguous into a memory range. Recording range translations can greatly increase the {TLB} reach, but ranges are also hard to index because they have arbitrary bounds. The processor has to compare against all the boundaries to determine which range an address falls in, which restricts the usage of memory ranges.
In this article, we propose a tagged-pointer-based scheme, {FlexPointer}, to solve the range indexing problem. The core insight of {FlexPointer} is that large memory objects are rare, so we can create memory ranges based on such objects and assign each of them a unique {ID}. With the range {ID} integrated into pointers, we can index the range {TLB} with {IDs} and greatly simplify its structure. Moreover, because the {ID} is stored in the unused bits of a pointer and is not manipulated by the address generation, we can shift the range lookup to an earlier stage, working in parallel with the address generation. According to our trace-based simulation results, {FlexPointer} can reduce nearly all the L1 {TLB} misses, and page walks for a variety of memory-intensive workloads. Compared with a 4K-page baseline system, {FlexPointer} shows a 14\% performance improvement on average and up to 2.8x speedup in the best case. For other workloads, {FlexPointer} shows no performance degradation.},
pages = {1--24},
number = {2},
journaltitle = {{ACM} Transactions on Architecture and Code Optimization},
shortjournal = {{ACM} Trans. Archit. Code Optim.},
author = {Chen, Dongwei and Tong, Dong and Yang, Chun and Yi, Jiangfang and Cheng, Xu},
urldate = {2024-05-27},
date = {2023-06-30},
langid = {english},
file = {Full Text PDF:/Users/akilan/Zotero/storage/L9XGZDFK/Chen et al. - 2023 - FlexPointer Fast Address Translation Based on Ran.pdf:application/pdf},
author = {Chen, Dongwei and Tong, Dong and Yang, Chun and Yi, Jiangfang and Cheng, Xu},
title = {FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers},
year = {2023},
issue_date = {June 2023},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {20},
number = {2},
issn = {1544-3566},
url = {https://doi.org/10.1145/3579854},
doi = {10.1145/3579854},
abstract = {Page-based virtual memory relies on TLBs to accelerate the address translation. Nowadays, the gap between application workloads and the capacity of TLB continues to grow, bringing many costly TLB misses and making the TLB a performance bottleneck. Previous studies seek to narrow the gap by exploiting the contiguity of physical pages. One promising solution is to group pages that are both virtually and physically contiguous into a memory range. Recording range translations can greatly increase the TLB reach, but ranges are also hard to index because they have arbitrary bounds. The processor has to compare against all the boundaries to determine which range an address falls in, which restricts the usage of memory ranges. In this article, we propose a tagged-pointer-based scheme, FlexPointer, to solve the range indexing problem. The core insight of FlexPointer is that large memory objects are rare, so we can create memory ranges based on such objects and assign each of them a unique ID. With the range ID integrated into pointers, we can index the range TLB with IDs and greatly simplify its structure. Moreover, because the ID is stored in the unused bits of a pointer and is not manipulated by the address generation, we can shift the range lookup to an earlier stage, working in parallel with the address generation. According to our trace-based simulation results, FlexPointer can reduce nearly all the L1 TLB misses, and page walks for a variety of memory-intensive workloads. Compared with a 4K-page baseline system, FlexPointer shows a 14\% performance improvement on average and up to 2.8x speedup in the best case. For other workloads, FlexPointer shows no performance degradation.},
journal = {ACM Trans. Archit. Code Optim.},
month = mar,
articleno = {30},
numpages = {24},
keywords = {Tagged pointer, TLB reach, address translation}
}
@article{woodruff_cheri_2019,
@@ -187,12 +199,13 @@ keywords = {tanslation lookaside buffer, virtual memory}
file = {Curtsinger and Berger - 2015 - Coz Finding Code that Counts with Causal Profilin.pdf:/Users/akilan/Zotero/storage/QTFQXVHE/Curtsinger and Berger - 2015 - Coz Finding Code that Counts with Causal Profilin.pdf:application/pdf},
}
@online{noauthor_benchmark_nodate,
title = {Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial},
url = {https://www.cheribsd.org/tutorial/23.11/benchmark/index.html},
urldate = {2024-06-07},
file = {Benchmark ABI - CheriBSD 23.11 new features tutorial:/Users/akilan/Zotero/storage/9BDKUW28/index.html:text/html},
}
@online{noauthor_benchmark_nodate,
title = {Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial},
url = {https://www.cheribsd.org/tutorial/23.11/benchmark/index.html},
howpublished = "\url{https://www.cheribsd.org/tutorial/23.11/benchmark/index.html}",
urldate = {2024-06-07},
file = {Benchmark ABI - CheriBSD 23.11 new features tutorial:/Users/akilan/Zotero/storage/9BDKUW28/index.html:text/html},
}
@inproceedings{zhu_research_2018,
location = {Taipei, Taiwan},
@@ -502,11 +515,11 @@ keywords = {tanslation lookaside buffer, virtual memory}
number = {UCAM-CL-TR-986}
}
@online{jemalloc,
title = {{JEMALLOC}},
url = {https://jemalloc.net/jemalloc.3.html},
urldate = {2025-01-15},
file = {JEMALLOC:/Users/akilan/Zotero/storage/QDEIEJ9N/jemalloc.3.html:text/html},
@inproceedings{jemalloc,
title={A scalable concurrent malloc (3) implementation for FreeBSD},
author={Evans, Jason},
booktitle={Proc. of the bsdcan conference, ottawa, canada},
year={2006}
}
@online{Benchmark,
@@ -549,6 +562,22 @@ pages = {129–139},
numpages = {11}
}
@inproceedings{IntelItanium,
author = {Cornea, Marius and Harrison, John and Tang, Ping Tak Peter},
title = {Intel® Itanium® floating-point architecture},
year = {2003},
isbn = {9781450347327},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/1275521.1275526},
doi = {10.1145/1275521.1275526},
abstract = {The Intel® Itanium® architecture is increasingly becoming one of the major processor architectures present in the market today. Launched in 2001, the Intel Itanium processor was followed in 2002 by the Itanium 2 processor, with increased integer and floating-point performance. Measured by the SPEC CINT2000 benchmarks, the Itanium 2 processor still trails by about 25\% the Intel P4 processor in integer performance, albeit P4 runs at more than three times Itanium's clock frequency. However, its floating-point performance clearly leads in the SPEC CFP2000 charts, and its rating is about 25\% higher than that of the P4 processor. While the general features of the Itanium architecture such as large register sets, predication, speculation, and support for explicit parallelism [1] have been presented in several papers, books, and mainstream college textbooks [2], its floating-point architecture has been less publicized. Two books, [3] and [4], cover well this area. The present paper focuses on the floating-point architecture of the Itanium processor family, and points out a few remarkable features suitable to be the focus of a lecture, lab session, or project in a computer architecture class.},
booktitle = {Proceedings of the 2003 Workshop on Computer Architecture Education: Held in Conjunction with the 30th International Symposium on Computer Architecture},
pages = {3–es},
location = {San Diego, California},
series = {WCAE '03}
}
@phdthesis{singh1993,
author = {Singh, Jaswinder Pal},
title = {Parallel Hierarchical N-body Methods and Their Implications for Multiprocessors},