added plan-1 and saved changes

docs/FutureTasks/Plan/gnatt-chart.py

@@ -0,0 +1,55 @@
+import matplotlib.pyplot as plt
+import matplotlib.dates as mdates
+from datetime import datetime
+import pandas as pd
+
+# Define updated tasks and durations
+updated_tasks = [
+    ("Refactor BSV modules", "2025-06-01", "2025-07-01"),
+    ("Setup C benchmark suite", "2025-06-01", "2025-07-01"),
+    ("EuroSys paper revisions (feedback)", "2025-06-01", "2025-07-31"),
+    ("Formal progression review", "2025-06-01", "2025-07-01"),
+    ("Submit EuroSys for preliminary feedback", "2025-06-01", "2025-07-01"),
+    ("Debug Toooba memory pipeline (TLB bypass)", "2025-07-01", "2025-08-31"),
+    ("Validate C benchmark suite", "2025-07-01", "2025-08-01"),
+    ("Documentation for second paper", "2025-07-15", "2025-08-31"),
+    ("Finalise EuroSys revisions", "2025-07-01", "2025-07-31"),
+    ("Continue memory debugging", "2025-08-01", "2025-09-30"),
+    ("Draft second paper (intro/method)", "2025-08-01", "2025-09-30"),
+    ("Generate experimental results", "2025-08-15", "2025-09-30"),
+    ("Publish EuroSys paper", "2025-09-01", "2025-10-01"),
+    ("Benchmark Toooba design", "2025-09-01", "2025-10-31"),
+    ("Draft eval & analysis (second paper)", "2025-09-15", "2025-10-31"),
+    ("Third experimental phase", "2025-10-01", "2025-11-30"),
+    ("Modify allocators (remove mmap)", "2025-10-15", "2025-11-30"),
+    ("Finalise second paper", "2025-11-01", "2025-11-30"),
+    ("Strip huge-page optimisations", "2025-11-01", "2025-12-31"),
+    ("Analyse instruction-level reductions", "2025-11-01", "2025-12-31"),
+    ("Draft third research paper", "2025-11-15", "2025-12-31"),
+    ("Evaluate/profile third paper", "2025-12-01", "2026-01-31"),
+    ("Write thesis chapters (Exp 1 & 2)", "2025-12-15", "2026-01-31"),
+    ("Thesis development & refinement", "2026-01-01", "2026-09-30"),
+    ("Submit third paper", "2026-01-01", "2026-09-30"),
+    ("Prepare full dissertation", "2026-01-01", "2026-09-30"),
+]
+
+# Convert to DataFrame
+df = pd.DataFrame(updated_tasks, columns=["Task", "Start", "End"])
+df["Start"] = pd.to_datetime(df["Start"])
+df["End"] = pd.to_datetime(df["End"])
+df["Duration"] = df["End"] - df["Start"]
+
+# Plot
+fig, ax = plt.subplots(figsize=(14, 12))
+for i, row in df.iterrows():
+    ax.barh(i, row["Duration"].days, left=row["Start"], height=0.8)
+
+ax.set_yticks(range(len(df)))
+ax.set_yticklabels(df["Task"])
+ax.xaxis.set_major_locator(mdates.MonthLocator())
+ax.xaxis.set_major_formatter(mdates.DateFormatter("%b %Y"))
+plt.xticks(rotation=45)
+plt.title("PhD Gantt Chart: June 2025 – September 2026")
+plt.tight_layout()
+plt.grid(axis='x')
+plt.show()

docs/FutureTasks/Plan/plan-1.org

@@ -1,90 +1,106 @@
 * Plan
 This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year.
 
-** Link to Previous PhD Plan
-https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf
+** Current experiments:
+1. FAT allocator with huge pages.
+2. FAT allocator to bypass TLB.
+3. Allocator evaluation based on stripping instruction calls for larger allocators.
+
+** Experiment cancelled:
+1. Uni-Kernel Development: Work scaled down to fit within the allocated PhD timeframe and introduced an extension of the FAT allocator as the third experiment.
+
+** Link to the Previous PhD Plan
+- https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf
 
 ** Summary of the Previous Plan
-
 *** Phase 1: FAT-Pointer Mechanism (July–September 2024)
-**** 1st–15th July 2024
+**** 1st to 15th July 2024
 - Investigated causes of L1 TLB misses associated with contiguous memory allocation.
 - Executed performance benchmarking using COZ on selected C programs.
 - Ported the kernel module to support SnMalloc, the default allocator in CheriBSD.
 
-**** 15th–30th July 2024
+**** 15th to 30th July 2024
 - Conducted benchmarking using the SPEC and XSBench suites.
 - Performed comparative analysis with both baseline and modified SnMalloc implementations.
 
-**** August 2024
-- Initiated drafting of a manuscript for submission to EuroSys, focusing on the FAT-Pointer memory allocator.
+**** August 2024 
+- Initiated drafting of a paper for submission to EuroSys, focusing on the FAT-Pointer memory allocator.
 
 **** September 2024
 - Compiled and structured thesis chapter related to the FAT-Pointer architecture.
 - Finalised and submitted the EuroSys paper.
 
 *** Phase 2: RISC-V Integration (October 2024 – May 2025)
-**** October–December 2024
+**** October to December 2024
 - Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline.
 - Configured the experimental platform and evaluation toolchain.
 
-**** January–February 2025
+**** January to February 2025
 - Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba).
 - Commenced drafting of a technical paper for ISMM based on RISC-V integration results.
 
-**** March–May 2025
+**** March to May 2025
 - Addressed outstanding tasks and technical backlog.
 - Continued development of the corresponding thesis chapter.
 
 *** Phase 3: Uni-Kernel Deployment (May 2025 – September 2026)
-**** May–December 2025
+**** May to December 2025
 - Ported the memory allocator to a CHERI-enabled Uni-Kernel environment.
 - Designed and implemented a unified memory allocator to support both kernel and user-level allocations.
 - Initiated drafting of a manuscript targeted at OSDI.
 
-**** January–September 2026
+**** January to September 2026
 - Finalised documentation and submission of the PhD thesis.
 - Submitted third research paper based on extended evaluation.
 
 ** Current Research Plan
+This section outlines a comprehensive timeline of research activities and academic milestones undertaken between June 
+2025 and September 2026 as part of the PhD focused on the CHERI Toooba architecture. It includes the refactoring of BlueSpec SystemVerilog modules and the development of a bare-metal 
+C benchmark suite. The work involves in-depth 
+debugging of the Toooba memory subsystem, the design and evaluation of in-depth analyses of the FAT allocator and performance analysis at the instruction 
+level. Alongside these technical efforts, the timeline reflects the structured drafting of academic publications and the ongoing development 
+of the PhD thesis leading to the final submission of the dissertation.
 
-*** June–July 2025
+[[./gnatt-chart.png]]
+
+*** June to July 2025
 - Refactored BlueSpec SystemVerilog (BSV) modules within the CHERI Toooba architecture.
 - Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform.
 - Incorporated supervisory team feedback into revisions of the EuroSys paper.
 - Undertook formal progression review requirements.
 - Submitted EuroSys manuscript to the CHERI research team at the University of Glasgow for preliminary feedback.
 
-*** July–August 2025
+*** July to August 2025
 - Engaged in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path.
 - Finalised and validated the C benchmark suite for Toooba evaluation.
 - Began technical documentation of the Toooba workflow, to support a second publication.
 - Concluded revisions to the EuroSys paper by the end of July.
 
-*** August–September 2025
+*** August to September 2025
 - Continued debugging efforts within the Toooba memory subsystem.
 - Drafted the abstract, introduction, and methodology sections of the second research paper.
 - Aimed to generate preliminary experimental results for inclusion in the evaluation.
 
-*** September–October 2025
+*** September to October 2025
 - Published the EuroSys paper detailing the FAT-Pointer allocator.
 - Commenced benchmarking of the Toooba design.
 - Simultaneously drafted the evaluation and analysis sections of the second manuscript.
 
-*** October–November 2025
+*** October to November 2025
 - Initiated third experimental phase, aimed at deeper evaluation of prior experiments.
 - Modified memory allocators (TcMalloc and Mesh) to remove reliance on `mmap`.
 
-*** November–December 2025
+*** November to December 2025
+- Finalised second paper for peer review.
 - Stripped away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh.
 - Analysed instruction-level reductions and performance implications.
 - Commenced drafting of the third research paper, building on contributions from the EuroSys paper.
 
-*** December 2025 – January 2026
+*** December 2025 to January 2026
 - Conducted evaluation and profiling for the third paper.
 - Commenced thesis chapter write-up for Experiments 1 and 2.
 
-*** January–September 2026
+*** January to September 2026
 - Continued thesis development and refinement across all experimental chapters.
-- Finalised and submitted third manuscript for peer review.
+- Finalised and submitted third paper for peer review.
 - Prepared complete PhD dissertation for submission.

docs/FutureTasks/Plan/plan-1.tex

@@ -1,4 +1,4 @@
-% Created 2025-06-11 Wed 22:18
+% Created 2025-06-16 Mon 15:56
 % Intended LaTeX compiler: pdflatex
 \documentclass[11pt]{article}
 \usepackage[utf8]{inputenc}
@@ -27,86 +27,108 @@
 \tableofcontents
 
 \section{Plan}
-\label{sec:org0566484}
+\label{sec:orgafd9b66}
 This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year.
-\subsection{Link to Previous PhD Plan}
-\label{sec:org9f71b80}
-\url{https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf}
-\subsection{Summary of the Previous Plan}
-\label{sec:orgaa32ef2}
-
-\subsubsection{Phase 1: FAT-Pointer Mechanism (July–September 2024)}
-\label{sec:org947ff17}
+\subsection{Current experiments:}
+\label{sec:orgf6e97da}
 \begin{enumerate}
-\item 1st–15th July 2024
-\label{sec:org4686601}
+\item FAT allocator with huge pages.
+\item FAT allocator to bypass TLB.
+\item Allocator evaluation based on stripping instruction calls for larger allocators.
+\end{enumerate}
+\subsection{Experiment cancelled:}
+\label{sec:orga64de5d}
+\begin{enumerate}
+\item Uni-Kernel Development: Work scaled down to fit within the allocated PhD timeframe and introduced an extension of the FAT allocator as the third experiment.
+\end{enumerate}
+\subsection{Link to the Previous PhD Plan}
+\label{sec:org3edf6e4}
+\begin{itemize}
+\item \url{https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf}
+\end{itemize}
+\subsection{Summary of the Previous Plan}
+\label{sec:orgbd2e628}
+\subsubsection{Phase 1: FAT-Pointer Mechanism (July–September 2024)}
+\label{sec:org602d9b9}
+\begin{enumerate}
+\item 1st to 15th July 2024
+\label{sec:orgb53cc89}
 \begin{itemize}
 \item Investigated causes of L1 TLB misses associated with contiguous memory allocation.
 \item Executed performance benchmarking using COZ on selected C programs.
 \item Ported the kernel module to support SnMalloc, the default allocator in CheriBSD.
 \end{itemize}
-\item 15th–30th July 2024
-\label{sec:orgb1cc375}
+\item 15th to 30th July 2024
+\label{sec:org7864ac1}
 \begin{itemize}
 \item Conducted benchmarking using the SPEC and XSBench suites.
 \item Performed comparative analysis with both baseline and modified SnMalloc implementations.
 \end{itemize}
 \item August 2024
-\label{sec:orgc7132f0}
+\label{sec:org49e9675}
 \begin{itemize}
-\item Initiated drafting of a manuscript for submission to EuroSys, focusing on the FAT-Pointer memory allocator.
+\item Initiated drafting of a paper for submission to EuroSys, focusing on the FAT-Pointer memory allocator.
 \end{itemize}
 \item September 2024
-\label{sec:org735895d}
+\label{sec:org1aae812}
 \begin{itemize}
 \item Compiled and structured thesis chapter related to the FAT-Pointer architecture.
 \item Finalised and submitted the EuroSys paper.
 \end{itemize}
 \end{enumerate}
 \subsubsection{Phase 2: RISC-V Integration (October 2024 – May 2025)}
-\label{sec:orgd874419}
+\label{sec:org74c2673}
 \begin{enumerate}
-\item October–December 2024
-\label{sec:orgc01cd5d}
+\item October to December 2024
+\label{sec:org6994353}
 \begin{itemize}
 \item Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline.
 \item Configured the experimental platform and evaluation toolchain.
 \end{itemize}
-\item January–February 2025
-\label{sec:org2f43abb}
+\item January to February 2025
+\label{sec:org71f7755}
 \begin{itemize}
 \item Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba).
 \item Commenced drafting of a technical paper for ISMM based on RISC-V integration results.
 \end{itemize}
-\item March–May 2025
-\label{sec:orgca33d11}
+\item March to May 2025
+\label{sec:org19387dc}
 \begin{itemize}
 \item Addressed outstanding tasks and technical backlog.
 \item Continued development of the corresponding thesis chapter.
 \end{itemize}
 \end{enumerate}
 \subsubsection{Phase 3: Uni-Kernel Deployment (May 2025 – September 2026)}
-\label{sec:org03fcd08}
+\label{sec:org4ec1211}
 \begin{enumerate}
-\item May–December 2025
-\label{sec:org2cdb782}
+\item May to December 2025
+\label{sec:orgebc4f5e}
 \begin{itemize}
 \item Ported the memory allocator to a CHERI-enabled Uni-Kernel environment.
 \item Designed and implemented a unified memory allocator to support both kernel and user-level allocations.
 \item Initiated drafting of a manuscript targeted at OSDI.
 \end{itemize}
-\item January–September 2026
-\label{sec:org004e3d6}
+\item January to September 2026
+\label{sec:org69a9a4b}
 \begin{itemize}
 \item Finalised documentation and submission of the PhD thesis.
 \item Submitted third research paper based on extended evaluation.
 \end{itemize}
 \end{enumerate}
 \subsection{Current Research Plan}
-\label{sec:orgd8dd9c2}
+\label{sec:org4597631}
+This section outlines a comprehensive timeline of research activities and academic milestones undertaken between June 
+2025 and September 2026 as part of the PhD focused on the CHERI Toooba architecture. It includes the refactoring of BlueSpec SystemVerilog modules and the development of a bare-metal 
+C benchmark suite. The work involves in-depth 
+debugging of the Toooba memory subsystem, the design and evaluation of in-depth analyses of the FAT allocator and performance analysis at the instruction 
+level. Alongside these technical efforts, the timeline reflects the structured drafting of academic publications and the ongoing development 
+of the PhD thesis leading to the final submission of the dissertation.
 
-\subsubsection{June–July 2025}
-\label{sec:org6d3b5a5}
+\begin{center}
+\includegraphics[width=.9\linewidth]{./gnatt-chart.png}
+\end{center}
+\subsubsection{June to July 2025}
+\label{sec:org95e44ac}
 \begin{itemize}
 \item Refactored BlueSpec SystemVerilog (BSV) modules within the CHERI Toooba architecture.
 \item Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform.
@@ -114,52 +136,53 @@ This document outlines the proposed PhD research plan for the forthcoming academ
 \item Undertook formal progression review requirements.
 \item Submitted EuroSys manuscript to the CHERI research team at the University of Glasgow for preliminary feedback.
 \end{itemize}
-\subsubsection{July–August 2025}
-\label{sec:orgf0ae0c2}
+\subsubsection{July to August 2025}
+\label{sec:org3309e51}
 \begin{itemize}
 \item Engaged in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path.
 \item Finalised and validated the C benchmark suite for Toooba evaluation.
 \item Began technical documentation of the Toooba workflow, to support a second publication.
 \item Concluded revisions to the EuroSys paper by the end of July.
 \end{itemize}
-\subsubsection{August–September 2025}
-\label{sec:org81af15d}
+\subsubsection{August to September 2025}
+\label{sec:orgd4ef96b}
 \begin{itemize}
 \item Continued debugging efforts within the Toooba memory subsystem.
 \item Drafted the abstract, introduction, and methodology sections of the second research paper.
 \item Aimed to generate preliminary experimental results for inclusion in the evaluation.
 \end{itemize}
-\subsubsection{September–October 2025}
-\label{sec:org4296fa4}
+\subsubsection{September to October 2025}
+\label{sec:orged09227}
 \begin{itemize}
 \item Published the EuroSys paper detailing the FAT-Pointer allocator.
 \item Commenced benchmarking of the Toooba design.
 \item Simultaneously drafted the evaluation and analysis sections of the second manuscript.
 \end{itemize}
-\subsubsection{October–November 2025}
-\label{sec:org6827c47}
+\subsubsection{October to November 2025}
+\label{sec:org4041d7a}
 \begin{itemize}
 \item Initiated third experimental phase, aimed at deeper evaluation of prior experiments.
 \item Modified memory allocators (TcMalloc and Mesh) to remove reliance on `mmap`.
 \end{itemize}
-\subsubsection{November–December 2025}
-\label{sec:orgab49ede}
+\subsubsection{November to December 2025}
+\label{sec:org5a08a2c}
 \begin{itemize}
+\item Finalised second paper for peer review.
 \item Stripped away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh.
 \item Analysed instruction-level reductions and performance implications.
 \item Commenced drafting of the third research paper, building on contributions from the EuroSys paper.
 \end{itemize}
-\subsubsection{December 2025 – January 2026}
-\label{sec:org28a1815}
+\subsubsection{December 2025 to January 2026}
+\label{sec:org2e22325}
 \begin{itemize}
 \item Conducted evaluation and profiling for the third paper.
 \item Commenced thesis chapter write-up for Experiments 1 and 2.
 \end{itemize}
-\subsubsection{January–September 2026}
-\label{sec:org3b950ac}
+\subsubsection{January to September 2026}
+\label{sec:orga5d12a0}
 \begin{itemize}
 \item Continued thesis development and refinement across all experimental chapters.
-\item Finalised and submitted third manuscript for peer review.
+\item Finalised and submitted third paper for peer review.
 \item Prepared complete PhD dissertation for submission.
 \end{itemize}
 \end{document}