saving current changes

.vscode/settings.json

@@ -62,7 +62,9 @@
         "cstdlib": "c",
         "cwchar": "c",
         "new": "c",
-        "param.h": "c"
+        "param.h": "c",
+        "pages.h": "c",
+        "jemalloc_malloc_pseudo_code": "c"
     },
     "C_Cpp.errorSquiggles": "disabled"
 }

benchmarks/benchmarks/StressTestMalloc/config.h

@@ -1,9 +1,10 @@
 #define NPAD 7
 #define MIN_WSS sizeof(struct l)
-#ifdef __MACH__
-#define MAX_WSS 4294967296 //2^31
-#else
-#define MAX_WSS 8589934592 //2^32
-#endif
+#define MAX_WSS 429496729
+// #ifdef __MACH__
+// #define MAX_WSS 4294967296 //2^31
+// #else
+// #define MAX_WSS 8589934592 //2^32
+// #endif
 
 #define NTHREADS 0 

benchmarks/benchmarks/StressTestMalloc/glibc-bench.c

@@ -207,10 +207,10 @@ main (int argc, char **argv)
 
   // bench (size);
   bench (2*size);
-  //bench (4*size);
+  // bench (4*size);
   //bench (8*size);
   // bench (16*size);
-  // bench (32*size); 
+  //bench (32*size); 
 
   return 0;
 }

benchmarks/benchmarks/StressTestMalloc/memaccesstest.c

@@ -266,10 +266,11 @@ void * walk(void *param)
 
 int main(int argc,char **argv)
 {
+clock_t tic = clock();
 // INITREGULARALLOC();
-#ifdef DEBUG
+//#ifdef DEBUG
 	printf("DEBUG:sizeof(struct l)=%ld\n",sizeof(struct l));
-#endif
+// #endif
 	struct l *root;
 	unsigned long working_set_size;
 	int i;
@@ -285,11 +286,16 @@ int main(int argc,char **argv)
 #ifdef DEBUG
 		printf("DEBUG:Working set size=%ld elements=%ld\n",working_set_size,working_set_size/sizeof(struct l));
 #endif
-
+clock_t toc = clock();
+printf("Elapsed build get here before ll: %f seconds\n", (double)(toc - tic) / CLOCKS_PER_SEC);
 #ifdef RANDOM_LIST
 		build_random_ll(root, working_set_size);
 #else
-		build_sequencial_ll(root, working_set_size);
+	clock_t tic1 = clock();
+	build_sequencial_ll(root, working_set_size);
+	// build_sequencial_ll(root, working_set_size);
+	clock_t toc1 = clock();
+	printf("Elapsed build ll: %f seconds\n", (double)(toc1 - tic1) / CLOCKS_PER_SEC);
 #endif
 
 #if NTHREADS>0			
@@ -309,11 +315,17 @@ int main(int argc,char **argv)
 		tdata->thread_index=0;
 		tdata->root=root;
 		tdata->working_set_size=working_set_size;
-		
-		walk((void*)tdata);	
+		clock_t tic2 = clock();
+		for (int i = 0; i < 8000; i++) {
+			walk((void*)tdata);	
+		}
+		clock_t toc2 = clock();
+		printf("Elapsed build walk: %f seconds\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC);
 #endif
 	}
 
+	printf("-----------------------------------------------");
+
 
 	// free(root);	
 

benchmarks/benchmarks/StressTestMalloc/memaccesstest.sh

@@ -1,3 +1,5 @@
 # sh build.sh
-LD_PRELOAD=./libjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o memaccesstest-cheri.stat ./memaccesstest.out
-LD_PRELOAD=./regularjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o memaccesstest-regular.stat ./memaccesstest.out
+# LD_PRELOAD=./libjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o memaccesstest-cheri-8000.stat ./memaccesstest.out
+# LD_PRELOAD=./regularjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o memaccesstest-regular-8000.stat ./memaccesstest.out
+
+time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o memaccesstest-regular-alloc-8000.stat ./memaccesstest.out

docs/EuroSys/Paper/build.sh

@@ -1 +1 @@
-latexmk -pdf paper.tex
+latexmk --shell-escape -pdf paper.tex

docs/EuroSys/Paper/drawio/jemalloc_malloc_pseudo_code

@@ -0,0 +1,72 @@
+static void *
+os_pages_map(void *addr, size_t size, size_t alignment, bool *commit) {
+	assert(ALIGNMENT_ADDR2BASE(addr, os_page) == (vaddr_t)addr);
+	assert(ALIGNMENT_CEILING(size, os_page) == size);
+	assert(size != 0);
+	/* Non-NULL addresses don't work in CheriABI */
+	if (addr != NULL)
+		return (NULL);
+
+	if (os_overcommits) {
+		*commit = true;
+	}
+
+	void *ret;
+
+		ret = MALLOCCHERI(size);
+	
+	assert(ret != NULL);
+
+	if (addr != NULL && ret != addr) {
+		/*
+		 * We succeeded in mapping memory, but not in the right place.
+		 */
+		os_pages_unmap(ret, size);
+		ret = NULL;
+	}
+}
+
+
+void *
+pages_map(void *addr, size_t size, size_t alignment, bool *commit) {
+	assert(alignment >= PAGE);
+	assert(ALIGNMENT_ADDR2BASE(addr, alignment) == (vaddr_t)addr);
+
+		if (size & ~CHERI_REPRESENTABLE_ALIGNMENT_MASK(size))
+			abort();
+
+		...
+
+		void *ret = MALLOCCHERI(size); // replaced instead of mmap
+
+		return ret;
+	
+}
+
+static bool
+pages_commit_impl(void *addr, size_t size, bool commit) {
+	assert(PAGE_ADDR2BASE(addr) == addr);
+	assert(PAGE_CEILING(size) == size);
+	    
+        ...
+
+		void *result = MALLOCCHERI(size); // replaced instead of mmap
+		if (result != addr) {
+			/*
+			 * We succeeded in mapping memory, but not in the right
+			 * place.
+			 */
+			os_pages_unmap(result, size);
+			return true;
+		}
+		return false;
+	
+}
+
+static void
+os_pages_unmap(void *addr, size_t size) {
+	assert(ALIGNMENT_ADDR2BASE(addr, os_page) == (vaddr_t)addr);
+	assert(ALIGNMENT_CEILING(size, os_page) == size);
+    
+   FREECHERI(addr);
+}

docs/EuroSys/Paper/paper.aux

@@ -1,19 +1,18 @@
 \relax 
+\providecommand{\transparent@use}[1]{}
 \providecommand\hyper@newdestlabel[2]{}
 \providecommand\HyField@AuxAddToFields[1]{}
 \providecommand\HyField@AuxAddToCoFields[2]{}
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 \citation{mittal_survey_2017}
 \citation{panwar_hawkeye_2019}
 \citation{woodruff_cheri_2014}
 \citation{woodruff_cheri_2019}
+\@writefile{toc}{\contentsline {section}{Abstract}{1}{section*.1}\protected@file@percent }
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 \citation{TLBReach}
 \citation{panwar_hawkeye_2019}
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-\@writefile{toc}{\contentsline {section}{Abstract}{1}{section*.1}\protected@file@percent }
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 \citation{IntelItanium}
 \citation{Shadow_superpages}
 \citation{DirectSegment}
@@ -22,83 +21,99 @@
 \citation{chen_flexpointer_2023}
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+\citation{jemalloc}
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+\newlabel{sub@fig:dtlb-walk}{{a}{7}{DTLB Walks}{figure.caption.5}{}}
+\newlabel{fig:l1tlb-reads}{{2b}{7}{L1 TLB Reads}{figure.caption.5}{}}
+\newlabel{sub@fig:l1tlb-reads}{{b}{7}{L1 TLB Reads}{figure.caption.5}{}}
+\newlabel{fig:l1tlb-refill}{{2c}{7}{L1 TLB Refill}{figure.caption.5}{}}
+\newlabel{sub@fig:l1tlb-refill}{{c}{7}{L1 TLB Refill}{figure.caption.5}{}}
+\newlabel{fig:l2tlb-reads}{{2d}{7}{L2 TLB Reads}{figure.caption.5}{}}
+\newlabel{sub@fig:l2tlb-reads}{{d}{7}{L2 TLB Reads}{figure.caption.5}{}}
+\newlabel{fig:ll-cache-rd}{{2e}{7}{LL Cache Reads}{figure.caption.5}{}}
+\newlabel{sub@fig:ll-cache-rd}{{e}{7}{LL Cache Reads}{figure.caption.5}{}}
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+\newlabel{sec:Analysis}{{7.4}{8}{Analysis}{subsection.7.4}{}}
 \bibstyle{unsrtnat}
 \bibdata{paperReferences}
-\bibcite{mittal_survey_2017}{{1}{}{{Mittal}}{{}}}
-\bibcite{panwar_hawkeye_2019}{{2}{}{{Panwar et~al.}}{{Panwar, Bansal, and Gopinath}}}
-\bibcite{woodruff_cheri_2014}{{3}{}{{Woodruff et~al.}}{{Woodruff, Watson, Chisnall, Moore, Anderson, Davis, Laurie, Neumann, Norton, and Roe}}}
-\bibcite{woodruff_cheri_2019}{{4}{}{{Woodruff et~al.}}{{Woodruff, Joannou, Xia, Fox, Norton, Chisnall, Davis, Gudka, Filardo, Markettos, Roe, Neumann, Watson, and Moore}}}
-\bibcite{TLBReach}{{5}{2014}{{Pham et~al.}}{{Pham, Bhattacharjee, Eckert, and Loh}}}
-\bibcite{THP}{{6}{2003}{{Navarro et~al.}}{{Navarro, Iyer, Druschel, and Cox}}}
-\bibcite{IntelItanium}{{7}{2003}{{Cornea et~al.}}{{Cornea, Harrison, and Tang}}}
-\bibcite{Shadow_superpages}{{8}{2001}{{Park and Park}}{{}}}
-\bibcite{DirectSegment}{{9}{2013}{{Basu et~al.}}{{Basu, Gandhi, Chang, Hill, and Swift}}}
-\bibcite{karakostas_redundant_2015}{{10}{}{{Karakostas et~al.}}{{Karakostas, Gandhi, Ayar, Cristal, Hill, {McKinley}, Nemirovsky, Swift, and Ünsal}}}
-\bibcite{chen_flexpointer_2023}{{11}{2023}{{Chen et~al.}}{{Chen, Tong, Yang, Yi, and Cheng}}}
-\bibcite{jemalloc}{{12}{2006}{{Evans}}{{}}}
-\bibcite{cheribsd}{{13}{}{{che}}{{}}}
-\bibcite{Benchmark}{{14}{}{{Ben}}{{}}}
-\bibcite{Morello}{{15}{}{{Mor}}{{}}}
-\bibcite{BenchmarkABI}{{16}{2023}{{Watson et~al.}}{{Watson, Clarke, Sewell, Woodruff, Moore, Barnes, Grisenthwaite, Stacer, Baranga, and Richardson}}}
-\bibcite{PerformanceCounter}{{17}{}{{Per}}{{}}}
-\bibcite{singh1993}{{18}{1993}{{Singh}}{{}}}
-\bibcite{holt1995}{{19}{1995}{{Holt and Singh}}{{}}}
+\bibcite{TLBHierarchy}{{1}{2013}{{Lustig et~al.}}{{Lustig, Bhattacharjee, and Martonosi}}}
+\bibcite{mittal_survey_2017}{{2}{}{{Mittal}}{{}}}
+\bibcite{panwar_hawkeye_2019}{{3}{}{{Panwar et~al.}}{{Panwar, Bansal, and Gopinath}}}
+\bibcite{woodruff_cheri_2014}{{4}{}{{Woodruff et~al.}}{{Woodruff, Watson, Chisnall, Moore, Anderson, Davis, Laurie, Neumann, Norton, and Roe}}}
+\bibcite{woodruff_cheri_2019}{{5}{}{{Woodruff et~al.}}{{Woodruff, Joannou, Xia, Fox, Norton, Chisnall, Davis, Gudka, Filardo, Markettos, Roe, Neumann, Watson, and Moore}}}
+\bibcite{TLBReach}{{6}{2014}{{Pham et~al.}}{{Pham, Bhattacharjee, Eckert, and Loh}}}
+\bibcite{THP}{{7}{2003}{{Navarro et~al.}}{{Navarro, Iyer, Druschel, and Cox}}}
+\bibcite{IntelItanium}{{8}{2003}{{Cornea et~al.}}{{Cornea, Harrison, and Tang}}}
+\bibcite{Shadow_superpages}{{9}{2001}{{Park and Park}}{{}}}
+\bibcite{DirectSegment}{{10}{2013}{{Basu et~al.}}{{Basu, Gandhi, Chang, Hill, and Swift}}}
+\bibcite{karakostas_redundant_2015}{{11}{}{{Karakostas et~al.}}{{Karakostas, Gandhi, Ayar, Cristal, Hill, {McKinley}, Nemirovsky, Swift, and Ünsal}}}
+\bibcite{chen_flexpointer_2023}{{12}{2023}{{Chen et~al.}}{{Chen, Tong, Yang, Yi, and Cheng}}}
+\bibcite{jemalloc}{{13}{2006}{{Evans}}{{}}}
+\bibcite{cheribsd}{{14}{}{{che}}{{}}}
+\bibcite{Benchmark}{{15}{}{{Ben}}{{}}}
+\bibcite{Morello}{{16}{}{{Mor}}{{}}}
+\bibcite{BenchmarkABI}{{17}{2023}{{Watson et~al.}}{{Watson, Clarke, Sewell, Woodruff, Moore, Barnes, Grisenthwaite, Stacer, Baranga, and Richardson}}}
+\bibcite{PerformanceCounter}{{18}{}{{Per}}{{}}}
+\bibcite{singh1993}{{19}{1993}{{Singh}}{{}}}
+\bibcite{holt1995}{{20}{1995}{{Holt and Singh}}{{}}}
 \newlabel{tocindent-1}{0pt}
 \newlabel{tocindent0}{0pt}
 \newlabel{tocindent1}{4.185pt}
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-\newlabel{TotPages}{{8}{8}{}{page.8}{}}
-\gdef \@abspage@last{8}
+\@writefile{toc}{\contentsline {section}{\numberline {8}Conclusion}{9}{section.8}\protected@file@percent }
+\@writefile{toc}{\contentsline {section}{References}{9}{section*.7}\protected@file@percent }
+\newlabel{TotPages}{{9}{9}{}{page.9}{}}
+\gdef\svg@ink@ver@settings{{\m@ne }{inkscape}{\m@ne }}
+\gdef \@abspage@last{9}

docs/EuroSys/Paper/paper.bbl

@@ -1,10 +1,19 @@
-\begin{thebibliography}{19}
+\begin{thebibliography}{20}
 \providecommand{\natexlab}[1]{#1}
 \providecommand{\url}[1]{\texttt{#1}}
 \expandafter\ifx\csname urlstyle\endcsname\relax
   \providecommand{\doi}[1]{doi: #1}\else
   \providecommand{\doi}{doi: \begingroup \urlstyle{rm}\Url}\fi
 
+\bibitem[Lustig et~al.(2013)Lustig, Bhattacharjee, and Martonosi]{TLBHierarchy}
+Daniel Lustig, Abhishek Bhattacharjee, and Margaret Martonosi.
+\newblock Tlb improvements for chip multiprocessors: Inter-core cooperative
+  prefetchers and shared last-level tlbs.
+\newblock \emph{ACM Trans. Archit. Code Optim.}, 10\penalty0 (1), April 2013.
+\newblock ISSN 1544-3566.
+\newblock \doi{10.1145/2445572.2445574}.
+\newblock URL \url{https://doi.org/10.1145/2445572.2445574}.
+
 \bibitem[Mittal()]{mittal_survey_2017}
 Sparsh Mittal.
 \newblock A survey of techniques for architecting {TLBs}.

docs/EuroSys/Paper/paper.blg

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---line 539 of file paperReferences.bib
+--line 559 of file paperReferences.bib
 Warning--empty journal in mittal_survey_2017
 Warning--empty year in mittal_survey_2017
 Warning--empty year in mittal_survey_2017
@@ -26,45 +26,45 @@ Warning--empty year in cheribsd
 Warning--empty year in Benchmark
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 Warning--empty year in PerformanceCounter
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+write$ -- 321
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docs/EuroSys/Paper/paper.tex

@@ -56,6 +56,12 @@
 \usepackage{grffile}
 \usepackage{hyperref}
 
+\usepackage{multicol}
+\usepackage{graphicx}
+\usepackage{subcaption}
+\usepackage{caption}
+\usepackage{svg}
+
 \lstset{basicstyle=\small\ttfamily,columns=fullflexible}
 
 %%
@@ -127,7 +133,7 @@
 %%
 %% The "title" commanSd has an optional parameter,
 %% allowing the author to define a "short title" to be used in page headers.
-\title{Fat Address Translations}
+\title{FAT allocator}
 
 %%
 %% The "author" command and its associated commands are used to define
@@ -240,12 +246,14 @@
   % addressing, we introduce a memory allocator that can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that 
   % our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications.
 
-  The increasing gap between workload memory requirements and the capacity of translation lookaside buffers (TLBs) means TLB misses 
-  are more frequent, costing additional clock cycles and impacting runtime performance. One solution that has been explored is to use physically contiguous 
-  memory in conjunction with huge pages. The contribution is an alternative approach by exploiting capability-based addressing in the 
-  CHERI architecture. This paper presents a new memory allocator which associates capabilities with memory pointers by integrating 
-  block-based allocations within huge pages. Our allocator reduces TLB misses by up to 90\%, which leads to decreasing runtime
-  for memory-intensive applications.
+  The increasing gap between workload memory requirements and the capacity of translation lookaside buffers (TLBs) in hardware cache management of modern processors means that TLB misses
+  are more frequent, costing additional clock cycles and impacting runtime performance. One solution that has been explored is to use physically contiguous
+  memory in conjunction with huge pages.
+
+  The contribution is an alternative approach by exploiting capability-based addressing in the
+  CHERI architecture. This paper presents a new memory allocator called Fat Address Translations (FAT) which associates capabilities with memory pointers by integrating
+  block-based allocations within huge pages. The FAT allocator when ran independently and embedded inside Jemalloc reduces walking the TLB hierarchy by upto 99%, which leads to decreasing runtimes
+  for memory read and write intensive applications.
 \end{abstract}
 
 %%
@@ -328,34 +336,42 @@
 % accelerating memory management operations.
 
 In computing, achieving high performance is an ongoing challenge, especially as
-applications handle increasingly memory intensive workloads. Memory management is a key factor
-in reducing the time it takes to access a memory region. Translation Lookaside Buffers (TLBs) 
-are crucial in speeding up memory access by caching recent
-memory address translations. A TLB is a specialised cache in the memory management unit (MMU),
+applications handle increasingly memory intensive workloads. Performance referring to memory access rather than compute bound. 
+Memory management is a key factor in reducing the time it takes to access a memory region. 
+A Translation Lookaside Buffer (TLB) is a specialised cache in the memory management unit (MMU),
 It reduces the time required to convert virtual addresses to physical addresses. When a program accesses
 data in memory, the MMU first checks the TLB for a matching entry and avoids the slow process of
-accessing the page tables situated in memory. However, as applications grow more complex, the fixed size of
-TLBs often cannot keep up, leading to more TLB misses and performance slowdowns~\cite{mittal_survey_2017}.
+accessing the page tables situated in memory.
+TLBs are crucial in speeding up memory access by caching recent
+memory address translations. The TLB hierarchy~\cite{TLBHierarchy} comprises of a smaller, faster L1 TLB situated close to the processor core and a larger 
+slightly slower L2 TLB, both of which are usually private to each core thereby reducing the latency associated with page table lookups. 
+However, as applications grow more complex the TLBs often cannot keep up with the number of translation entries leading to more TLB misses which requires walking
+the TLB hierarchy and this leads to performance slowdowns~\cite{mittal_survey_2017}.
 To tackle this issue, researchers have explored new solutions, including the use of
 huge pages~\cite{panwar_hawkeye_2019}.
 
 Huge pages also known as large pages allow for the allocation of memory in significantly larger chunks
-compared to traditional small pages, by reducing the number of TLB entries needed to access a given amount
+compared to traditional small pages by reducing the number of TLB entries needed to access a given amount
 of memory. Huge pages offer a potential avenue for optimising TLBs which are used by reducing the number
 of entries needed to map large memory regions. This not only decreases the frequency of
-TLB misses but also lowers the overhead associated with address translation. By minimising
-these bottlenecks, huge pages can improve system performance in aspects such as speeding
-up memory-intensive applications, reducing latency in data access and enhancing throughput for
-workloads that rely heavily on large datasets.
+TLB misses but also lowers the overhead associated with address translation and therefore minimising
+these bottlenecks.
+% huge pages can improve system performance in aspects such as speeding
+% up memory-intensive applications, reducing latency in data access and enhancing throughput for
+% workloads that rely heavily on large datasets.
 
 Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
-~\cite{woodruff_cheri_2014} architecture presents additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
+~\cite{woodruff_cheri_2014} which are pointers that are replaced with capabilities with 128-bit or 256-bit 
+encoding scheme which consists of both the address and metadata. The metadata includes bounds, permissions and validity of the pointer
+which forms a capability. This transformation enforces strict memory 
+safety as capabilities prevent arbitrary pointer arithmetic and unauthorised memory access.
+CHERI's capability-based addressing approach not
 only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
 operations. By integrating CHERI's compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages, one of the contribution is demonstrating that it is possible to track, manage
 large and physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces the TLB pressure by minimising the number of
 entries required to map extensive memory regions thereby decreasing TLB misses and improving address translation performance.
-Furthermore, this paper introduces Fat Address Translations(FAT) which accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous
-memory allocations. The contributions for the following paper are as follows:
+Furthermore, this paper introduces the Fat Address Translations(FAT) allocator which accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous
+memory allocations by emulating block allocations on physically contiguous memory to reduce the TLB pressure. The contributions for the following paper are as follows:
 \begin{itemize}
   \item \textbf{FAT Addresses Translations}: Introduces FAT that include memory bounds, allowing
   efficient tracking and management of physically contiguous memory regions (Section ~\ref{sec:FatPointerTranslations}).
@@ -369,8 +385,8 @@ memory allocations. The contributions for the following paper are as follows:
    (Section ~\ref{sec:MemoryAllocator}).
 \end{itemize} 
 
-Through comprehensive evaluation including micro and macro benchmarks, It demonstrates the allocator's ability
-to reduce TLB misses by up to 90\% which yields significant improvements in wall clock runtimes for memory-intensive
+Through evaluating micro and macro benchmarks, FAT though the use of CHERI's capabilities and huge pages demonstrates the allocator's ability
+to reduce TLB misses by up to 90\% which yields to improvements of wall clock runtimes by upto 6\% for memory-intensive
 applications. While its impact on larger and computation-heavy workloads is less pronounced.
 The proposed allocator shows strong potential for advancing memory management in scenarios requiring
 high memory throughput by reducing the address translation overhead.
@@ -508,12 +524,12 @@ in this implementation is the use of range addresses with CHERI CC~\cite{woodruf
 % mitigating issues related to memory fragmentation.
 % \end{itemize}
 
-\begin{figure*}[h]
-  \includegraphics[width=0.6\textwidth]{diagram/HighOverviewArchitecture.drawio.png}
+\begin{figure}[h]
+  \includegraphics[width=0.5\textwidth]{diagram/drawing_png.png}
   \caption{High overview architecture}
   \label{fig:HighOverviewArchitecture}
 % \end{minipage}
-\end{figure*}
+\end{figure}
 
 Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (\textit{malloc}) and the proposed FAT method. The standard approach involves a C program interacting with a custom allocator which uses 48-bit 
 virtual addresses and the TLB hierarchy (L1, L2 and L3 cache) to achieve non-contiguous allocation in physical memory. 
@@ -536,12 +552,12 @@ bounds within the pointers and as shown in the figure \ref{fig:HighOverviewArchi
 % number of TLB entries required.
 
 \subsection{Encoding Ranges as Bounds to the Pointer}
-\label{sec:RangeMemory}
-\begin{figure}[h]
-  \includegraphics[width=0.4\textwidth]{diagram/AllocationOverview24.png}
-  \caption{Range of memory}
-  \label{fig:RangeOfMemory}
-\end{figure}
+% \label{sec:RangeMemory}
+% \begin{figure}[h]
+%   \includegraphics[width=0.4\textwidth]{diagram/AllocationOverview24.png}
+%   \caption{Range of memory}
+%   \label{fig:RangeOfMemory}
+% \end{figure}
 % Integrating range bounds directly into FAT-pointers enables the CHERI architecture
 % to enforce memory access restrictions at the pointer level thus allowing
 % tracking of memory ranges on a pointer level. 
@@ -613,11 +629,11 @@ This approach offers a more flexible alternative to the traditional fixed-size T
 % achieve optimal memory access patterns, enhancing performance and efficiency.
 
 \subsection{Instrumenting Block-Based Allocators with Physically Contiguous Memory}
-\begin{figure}[h]
-  \includegraphics[width=0.4\textwidth]{diagram/TLBAccess.drawio.png}
-  \caption{FAT Address Translations using huge pages}
-  \label{fig:HugePages}
-\end{figure}
+% \begin{figure}[h]
+%   \includegraphics[width=0.4\textwidth]{diagram/TLBAccess.drawio.png}
+%   \caption{FAT Address Translations using huge pages}
+%   \label{fig:HugePages}
+% \end{figure}
 % To build up based on Section ~\ref{sec:RangeMemory} and ~\ref{sec:128bitCompressedBounds}.
 FAT is able to pre-allocate memory using huge pages and is able to mark smaller allocations
 using ranges by storing them as bounds within the pointer. Each of these memory ranges can be
@@ -738,7 +754,7 @@ efficient memory management but also demonstrate a practical use case of huge pa
   \end{algorithmic}
   \end{algorithm}
 
-  Algorithm \ref{alg:initAlloc} describes the initialisation of physically contiguous memory through the use of huge pages
+Algorithm \ref{alg:initAlloc} describes the initialisation of physically contiguous memory through the use of huge pages
 which is a mechanism supported by modern architectures to optimise memory management. The algorithm begins by
 allocating a fixed block of 1 GB physically contiguous memory. This decision is driven by the
 architectural constraints of contemporary systems, particularly ARM-based CPUs. Where 1 GB represents
@@ -746,6 +762,84 @@ the largest supported page size. By leveraging huge pages, the algorithm reduces
 with page table management and enhances memory access which is critical for performance-sensitive
 applications and kernel-level operations.
 
+\section{Embedding FAT allocator inside Jemalloc}
+This section describes about the FAT allocator implementation (Section \ref{sec:MemoryAllocator}) embedded inside Jemalloc. The objective here is to describe the changes needed
+for a block based allocator to use physically contigous memory with a block based strategy with the help of capability based addresses. 
+In the case of Jemalloc the only changes required was to replace the mmap with the \textit{malloc} function (Algorithm \ref{alg:malloc}) and
+for munmap the \textit{free} function (Algorithm \ref{alg:free}). 
+
+\begin{algorithm}
+  \caption{Modified Jemalloc Memory Mapping Routines}
+  \label{alg:JemallocMalloc}
+  \begin{algorithmic}[1]
+  
+  \Statex \textbf{Function:} \textsc{os\_pages\_map(addr, size, alignment, commit)}
+  \Require addr aligned to \texttt{os\_page}, size aligned to \texttt{os\_page}, size $\neq 0$
+  \Ensure If \texttt{addr} is non-NULL (CheriABI), return NULL
+  
+  \If{$\text{addr} \neq \text{NULL}$}
+      \State \Return NULL
+  \EndIf
+  
+  \If{os\_overcommits}
+      \State commit $\gets$ true
+  \EndIf
+  
+  \State ret $\gets$ \textbf{MALLOC}(size)
+  \State \textbf{assert}(ret $\neq$ NULL)
+  
+  \If{addr $\neq$ NULL \textbf{and} ret $\neq$ addr}
+      \State \texttt{os\_pages\_unmap}(ret, size)
+      \State ret $\gets$ NULL
+  \EndIf
+  
+  \State \Return ret
+  
+  \vspace{1em}
+  \Statex \textbf{Function:} \textsc{pages\_map(addr, size, alignment, commit)}
+  \Require alignment $\geq$ \texttt{PAGE}, addr aligned to alignment
+  
+  \State ret $\gets$ \textbf{MALLOC}(size)
+  
+  \State \Return ret
+  
+  \vspace{1em}
+  \Statex \textbf{Function:} \textsc{pages\_commit\_impl(addr, size, commit)}
+  \Require addr aligned to \texttt{PAGE}, size aligned to \texttt{PAGE}
+  
+  \State result $\gets$ \textbf{MALLOC}(size)
+  
+  \If{result $\neq$ addr}
+      \State \texttt{os\_pages\_unmap}(result, size)
+      \State \Return true
+  \EndIf
+  
+  \State \Return false
+  
+  \end{algorithmic}
+  \end{algorithm}
+
+The only function required to be replaced with Malloc was os\_pages\_map, 
+pages\_map and pages\_commit\_impl as show in
+algorithm \ref{alg:JemallocMalloc}.
+
+\begin{algorithm}
+\label{alg:JemallocFree}
+  \caption{os\_pages\_unmap}
+  \begin{algorithmic}[1]
+  \Require addr aligned to \texttt{os\_page}, size aligned to \texttt{os\_page}
+  \Ensure Memory region at \texttt{addr} is unmapped
+  \State \textbf{assert}(\texttt{ALIGNMENT\_ADDR2BASE}(addr, os\_page) $=$ \texttt{addr})
+  \State \textbf{assert}(\texttt{ALIGNMENT\_CEILING}(size, os\_page) $=$ size)
+        
+  \State \textbf{FREE}(addr)
+  \end{algorithmic}
+\end{algorithm}
+    
+The only function required to be replaced with Free was 
+os\_pages\_unmap as show in
+algorithm \ref{alg:JemallocFree}. 
+
 \section{Evaluation}
 \label{sec:Evaluation}
 Benchmarks of the FAT memory allocator against Jemalloc~\cite{jemalloc} was conducted.
@@ -909,32 +1003,164 @@ This extension is described by Holt and Singh ~\cite{holt1995}.
 \subsection{Results}
 \label{sec:Results}
 
-\begin{figure*}[h]
-\includegraphics[width=.9\linewidth]{diagram/bargraph.png}
-\caption{\label{fig:bargraph}Percentage difference between the modified memory allocator against the default system memory allocator}
+% \begin{figure}[b]
+%   \centering
+%   \begin{subfigure}{.5\textwidth}
+%       \centering
+%       \includegraphics[width=0.45\textwidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
+%   \end{subfigure}%
+%   \begin{subfigure}{.5\textwidth}
+%       \centering
+%       \includegraphics[width=0.45\textwidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
+%   \end{subfigure}
+%   \begin{subfigure}{.5\textwidth}
+%       \centering
+%       \includegraphics[width=0.45\textwidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
+%   \end{subfigure}%
+%   \begin{subfigure}{.5\textwidth}
+%       \centering
+%       \includegraphics[width=0.45\textwidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
+%   \end{subfigure}
+%   \begin{subfigure}{\textwidth}
+%       \raggedleft
+%       \includegraphics[width=0.45\textwidth]{IMAGE NAME}
+%   \end{subfigure}
+%   \caption[short]{A beautiful, well written caption}
+%   \end{figure}
+
+% \begin{figure*}
+%   \begin{multicols}{2}
+%       \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}\par 
+%       \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l1tlb-reads.png}\par 
+%       \end{multicols}
+%   \begin{multicols}{2}
+%       \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l1tlb-refill.png}\par
+%       \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l2tlb-reads.png}\par
+%   \end{multicols}
+%   \begin{multicols}{2}
+%     \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-ll-cache-rd.png}\par
+%     \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-wallclock.png}\par
+% \end{multicols}
+%   \caption{Benchmarks comparing the percentage difference between FAT }
+%   \end{figure*}
+
+\begin{figure*}
+  \begin{multicols}{2}
+    \begin{subfigure}{\linewidth}
+      \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
+      \caption{DTLB Walks}
+      \label{fig:dtlb-walk}
+    \end{subfigure}\par 
+    \begin{subfigure}{\linewidth}
+      \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l1tlb-reads.png}
+      \caption{L1 TLB Reads}
+      \label{fig:l1tlb-reads}
+    \end{subfigure}\par 
+  \end{multicols}
+
+  \begin{multicols}{2}
+    \begin{subfigure}{\linewidth}
+      \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l1tlb-refill.png}
+      \caption{L1 TLB Refill}
+      \label{fig:l1tlb-refill}
+    \end{subfigure}\par 
+    \begin{subfigure}{\linewidth}
+      \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-l2tlb-reads.png}
+      \caption{L2 TLB Reads}
+      \label{fig:l2tlb-reads}
+    \end{subfigure}\par 
+  \end{multicols}
+
+  \begin{multicols}{2}
+    \begin{subfigure}{\linewidth}
+      \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-ll-cache-rd.png}
+      \caption{LL Cache Reads}
+      \label{fig:ll-cache-rd}
+    \end{subfigure}\par 
+    \begin{subfigure}{\linewidth}
+      \includegraphics[width=\linewidth]{diagram/benchmarks-group/bargraph-large-wallclock.png}
+      \caption{Wall Clock Time}
+      \label{fig:wallclock}
+    \end{subfigure}\par 
+  \end{multicols}
+
+  \caption{Benchmarks comparing the percentage difference between FAT.}
+  \label{fig:benchmarks-group}
 \end{figure*}
 
-Figure \ref{fig:bargraph} highlights the performance comparison between the modified memory allocator and
+% \begin{figure*}[h]
+% \includegraphics[width=.9\linewidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
+% \caption{\label{fig:bargraph}Percentage difference between the modified memory allocator against the default system memory allocator}
+% \end{figure*}
+% \begin{figure*}[h]
+%   \includegraphics[width=.9\linewidth]{diagram/benchmarks-group/bargraph-large-dtlb-walk.png}
+%   \caption{\label{fig:bargrapwh}Percentage difference between the modified memory allocator against the default system memory allocator}
+%   \end{figure*}
+
+Figure \ref{fig:benchmarks-group} highlights the performance comparison between the modified memory allocator and
 Jemalloc, the default memory allocator. The FAT memory allocator is specifically optimised
 for use with huge pages and demonstrates a clear advantage in scenarios where memory allocation
 patterns benefit from its design. The results align with expectations, showcasing the impact
 of its capability to handle memory more efficiently by leveraging huge pages.
 
 \begin{itemize}
-  \item L1 DTLB reads: There was a noticeable reduction of L1 DTLB reads for kmeans of about an average of
-  4\% less than Jemalloc and for Glibc there was significant reduction of 50\% less than Jemalloc. 
+  \item L1 DTLB reads: L1 Data TLB reads are critical for achieving fast memory access, and a reduction 
+  in events that could signify misses or lead to further lookups is generally beneficial. FAT allocator consistently performed 
+  at the baseline level (100\%) across all benchmarks including Kmeans, Memaccess, Glibc, Richards, and Barnes. 
+  In contrast, FAT allocator embedded inside Jemalloc exhibited varied performance. It achieved a notable 14\% 
+  reduction in L1D TLB reads for Kmeans and a minor 3\% reduction for Barnes. More significantly, it 
+  led to a substantial 68\% reduction for Memaccess, a benchmark characterized by linked list traversals 
+  that can challenge memory access efficiency, and a 59\% reduction for Glibc, which involves numerous memory 
+  allocation and deallocation operations. For the Richards benchmark, however, no significant change was observed with 
+  FAT allocator embedded inside Jemalloc. These results suggest that FAT allocator embedded inside Jemalloc may arrange memory 
+  in a manner that enhances spatial locality at the page level, particularly for workloads like Memaccess and Glibc.
   
-  \item L2 DTLB reads: For all the benchmarks on figure \ref{fig:bargraph} there was on average 98\% 
-  reduction in L2 DTLB reads. This demonstrates that all the TLB translations are read at the L1 TLB 
-  cache. 
+  \item L2 DTLB reads: L2 Data TLB reads (or lookups) serve as a secondary cache for address translations, and, similar to L1 TLB, lower values are 
+  indicative of better performance. FAT allocator consistently performed at the baseline (100\%) for this metric across all benchmarks. 
+  FAT allocator embedded inside Jemalloc also showed no significant change for Kmeans, Memaccess, and Richards. However, for the Glibc benchmark, 
+  it achieved a significant reduction of 60\% in L2D TLB reads. This mirrors its L1D TLB improvement for Glibc and suggests that its 
+  strategy for page locality extends effectively to deeper levels of the TLB hierarchy for this particular benchmark, which is notable given 
+  Glibc's high frequency of malloc calls that stress memory management. A minor reduction of 3\% was also observed for the Barnes 
+  benchmark with FAT allocator embedded inside Jemalloc.
 
-  \item DTLB walks: Due to most of the TLB entries getting hit at the L1 DTLB, there is no need 
-  to walk the TLB cache hierarchy. This is shown by an average of 99\% reduction in DTLB walks.
+  \item DTLB walks: Data Translation Lookaside Buffer (dTLB) walks, which occur when a virtual-to-physical 
+  address translation is not found in the DTLB and a page table traversal is necessary, represent a performance 
+  cost; thus, fewer walks are preferable. In the observed tests, neither FAT allocator nor FAT allocator embedded inside Jemalloc 
+  demonstrated any significant deviation from the baseline performance (100\%) for this metric. 
+  This consistent behavior was noted across all benchmarks evaluated: Kmeans, Memaccess, Glibc, Richards, and Barnes. 
+  This outcome suggests that the memory allocation strategies employed by these allocators do not substantially alter the frequency 
+  of DTLB misses that necessitate page table walks within these specific workloads. Even for the Memaccess benchmark, 
+  which is designed with random list traversals that can stress TLB pressure, the impact on dTLB walks was negligible according to the provided graphs.
 
-  \item L1 DTLB refills: Since there are fewer DTLB walks and most reads are done at the L1 DTLB
-  layer there is no need for numerous TLB refills to take place. Our benchmarks show on average 
-  a 99\% reduction in DTLB refills.
+  \item L1 DTLB refills: L1 Data TLB refills are a direct consequence of L1D TLB misses, with fewer refills indicating better performance. 
+  Interestingly, despite the variations observed in L1D TLB reads for FAT allocator embedded inside Jemalloc, the L1D TLB refills metric 
+  remained at the baseline (100\%) for both FAT allocator and FAT allocator embedded inside Jemalloc. This consistent performance at baseline 
+  was observed across all tested benchmarks: Kmeans, Memaccess, Glibc, Richards, and Barnes. This outcome presents a point of potential inconsistency; 
+  if L1D TLB reads (interpreted as events related to misses or lookups that could lead to misses) are reduced, a corresponding decrease in actual 
+  refills would typically be expected. The absence of change in refills might suggest that the "reads" metric captures a wider range of TLB interaction 
+  events than solely those leading to refills, or perhaps the absolute number of critical misses resulting in refills was minimal to begin with and thus 
+  not significantly affected by the allocators in these tests.
 
+  \item Last-level cache: Last-Level Cache (LLC) read misses are crucial performance indicators, as they often result in slow data fetches 
+  from main memory; therefore, fewer misses are highly desirable. The performance on this metric varied significantly between the 
+  allocators and across benchmarks. FAT allocator was near baseline for Kmeans but caused an 18\% increase in misses for Memaccess (designed to stress cache ), 
+  a 30\% increase for Richards (many dynamic allocations and pointer manipulations ), and an 18\% increase for Barnes (uses pointer-based octrees ). However, 
+  FAT allocator achieved a significant 60\% reduction in misses for the Glibc benchmark, which involves active memory use post-allocation.
+  FAT allocator embedded inside Jemalloc showed a 75\% reduction in misses for Memaccess, a substantial improvement. Conversely, it led to an 18\% increase in 
+  misses for Kmeans, a massive 375\% increase for Glibc, and a 65\% increase for Barnes. For the Richards benchmark, its performance was at the baseline. 
+  This high variability indicates that memory placement strategies of the allocators interact diversely with the specific access patterns of each benchmark, 
+  such as the difference between the large data arrays in K-Means  versus the linked structures common in Memaccess  or Richards.
+
+  \item Wall clock: Wallclock time provides the ultimate measure of overall execution performance, where lower values (deviations below 100\%) indicate improvement. 
+  FAT allocator resulted in a 1\% speedup for Kmeans and a more significant 5\% speedup for Barnes. This improvement for Barnes was observed despite an increase 
+  in its LL cache misses, suggesting other factors such as reduced allocator overhead or better CPU pipeline utilization might have contributed. 
+  For Memaccess and Glibc, FAT allocator performed at the baseline. Notably, the substantial LL cache miss reduction seen with FAT allocator on Glibc did not 
+  translate into an overall speedup. It was about 1\% slower on Richards.
+  FAT allocator embedded inside Jemalloc was 4\% faster for Memaccess, aligning well with its significant LL cache miss reduction and L1D TLB improvements 
+  for that benchmark. It performed at baseline for Kmeans and was negligibly faster (0.5\%) for Richards. However, it was 15\% slower for Glibc, a slowdown 
+  consistent with the massive increase in LL cache misses observed. For Barnes, it resulted in an 8\% slowdown, which also correlates with its increased 
+  LL cache misses for that benchmark. These wallclock results underscore that improvements in a single specific memory subsystem metric do not always guarantee 
+  an overall application speedup, as the interplay of various factors determines the final performance.
   \end{itemize}
 
 A particularly striking observation is the significant reduction in data TLB walks,
@@ -958,31 +1184,31 @@ beyond memory allocation. Additionally,
 the benefits of huge pages may be less pronounced for these workloads, as they are often
 bottlenecked by factors such as computation or I/O rather than memory translation overhead.
 
-\begin{figure}[htbp]
-  \centering
-  \includegraphics[width=1.1\linewidth]{./diagram/kmeans.png}
-  \caption{\label{fig:org8683315}Kmeans COZ benchmark executed against various cluster sizes}
-\end{figure}
+% \begin{figure}[htbp]
+%   \centering
+%   \includegraphics[width=1.1\linewidth]{./diagram/kmeans.png}
+%   \caption{\label{fig:org8683315}Kmeans COZ benchmark executed against various cluster sizes}
+% \end{figure}
 
-The K-means algorithm was executed with varying cluster sizes as shown in figure~\ref{fig:org8683315}, to evaluate the performance difference
-between the FAT allocator and Jemalloc as the workload scales. This analysis
-aims to understand how the allocators optimisations, particularly its ability to manage memory
-more efficiently with huge pages, impact performance under different workload conditions.
+% The K-means algorithm was executed with varying cluster sizes as shown in figure~\ref{fig:org8683315}, to evaluate the performance difference
+% between the FAT allocator and Jemalloc as the workload scales. This analysis
+% aims to understand how the allocators optimisations, particularly its ability to manage memory
+% more efficiently with huge pages, impact performance under different workload conditions.
 
-For most cluster sizes tested, the percentage difference in performance remained relatively
-consistent. This indicates that the allocators efficiency scales predictably with increasing
-workload sizes. Suggesting a stable and uniform benefit across different configurations. The
-consistent performance gain is likely due to the allocators ability to minimise TLB misses
-and efficiently manage memory allocations for the centroid and data point structures used in
-the K-means algorithm.
+% For most cluster sizes tested, the percentage difference in performance remained relatively
+% consistent. This indicates that the allocators efficiency scales predictably with increasing
+% workload sizes. Suggesting a stable and uniform benefit across different configurations. The
+% consistent performance gain is likely due to the allocators ability to minimise TLB misses
+% and efficiently manage memory allocations for the centroid and data point structures used in
+% the K-means algorithm.
 
-However, an anomaly was observed at a cluster size of 200k, where the percentage difference
-deviated significantly from the trend. At this cluster size, the memory access patterns and allocation behavior may align in a way that
-temporarily offsets the advantages of the FAT allocator. For example, the memory layout
-might interact with system-level caching mechanisms or TLB behavior differently leading to an
-unexpected change in performance. Additionally, the increased complexity of managing a higher
-number of clusters might introduce computational overhead that overshadows the memory allocators
-optimisations.
+% However, an anomaly was observed at a cluster size of 200k, where the percentage difference
+% deviated significantly from the trend. At this cluster size, the memory access patterns and allocation behavior may align in a way that
+% temporarily offsets the advantages of the FAT allocator. For example, the memory layout
+% might interact with system-level caching mechanisms or TLB behavior differently leading to an
+% unexpected change in performance. Additionally, the increased complexity of managing a higher
+% number of clusters might introduce computational overhead that overshadows the memory allocators
+% optimisations.
 
 % This observation highlights the importance of testing across a range of workload sizes and
 % configurations to uncover edge cases or specific scenarios where performance deviates from the

docs/EuroSys/Paper/paperReferences.bib

@@ -1,3 +1,23 @@
+@article{TLBHierarchy,
+author = {Lustig, Daniel and Bhattacharjee, Abhishek and Martonosi, Margaret},
+title = {TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs},
+year = {2013},
+issue_date = {April 2013},
+publisher = {Association for Computing Machinery},
+address = {New York, NY, USA},
+volume = {10},
+number = {1},
+issn = {1544-3566},
+url = {https://doi.org/10.1145/2445572.2445574},
+doi = {10.1145/2445572.2445574},
+abstract = {Translation Lookaside Buffers (TLBs) are critical to overall system performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as Chip MultiProcessors (CMPs) become ubiquitous, TLB design and performance must be reevaluated. Our article begins by performing a thorough TLB performance evaluation of sequential and parallel benchmarks running on a real-world, modern CMP system using hardware performance counters. This analysis demonstrates the need for further improvement of TLB hit rates for both classes of application, and it also points out that the data TLB has a significantly higher miss rate than the instruction TLB in both cases.In response to the characterization data, we propose and evaluate both Inter-Core Cooperative (ICC) TLB prefetchers and Shared Last-Level (SLL) TLBs as alternatives to the commercial norm of private, per-core L2 TLBs. ICC prefetchers eliminate 19\% to 90\% of Data TLB (D-TLB) misses across parallel workloads while requiring only modest changes in hardware. SLL TLBs eliminate 7\% to 79\% of D-TLB misses for parallel workloads and 35\% to 95\% of D-TLB misses for multiprogrammed sequential workloads. This corresponds to 27\% and 21\% increases in hit rates as compared to private, per-core L2 TLBs, respectively, and is achieved this using even more modest hardware requirements.Because of their benefits for parallel applications, their applicability to sequential workloads, and their readily implementable hardware, SLL TLBs and ICC TLB prefetchers hold great promise for CMPs.},
+journal = {ACM Trans. Archit. Code Optim.},
+month = apr,
+articleno = {2},
+numpages = {38},
+keywords = {TLB prefetching, Translation lookaside buffer, performance evaluation, shared last-level TLB, simulation}
+}
+
 @article{Shadow_superpages,
 title = {Aggressive superpage support with the shadow memory and the partial-subblock TLB},
 journal = {Microprocessors and Microsystems},

docs/EuroSys/Paper/svg-inkscape/drawing_svg-tex.pdf_tex

@@ -0,0 +1,103 @@
+%% Creator: Inkscape 1.3 (0e150ed, 2023-07-21), www.inkscape.org
+%% PDF/EPS/PS + LaTeX output extension by Johan Engelen, 2010
+%% Accompanies image file 'drawing_svg-tex.pdf' (pdf, eps, ps)
+%%
+%% To include the image in your LaTeX document, write
+%%   \input{<filename>.pdf_tex}
+%%  instead of
+%%   \includegraphics{<filename>.pdf}
+%% To scale the image, write
+%%   \def\svgwidth{<desired width>}
+%%   \input{<filename>.pdf_tex}
+%%  instead of
+%%   \includegraphics[width=<desired width>]{<filename>.pdf}
+%%
+%% Images with a different path to the parent latex file can
+%% be accessed with the `import' package (which may need to be
+%% installed) using
+%%   \usepackage{import}
+%% in the preamble, and then including the image with
+%%   \import{<path to file>}{<filename>.pdf_tex}
+%% Alternatively, one can specify
+%%   \graphicspath{{<path to file>/}}
+%% 
+%% For more information, please see info/svg-inkscape on CTAN:
+%%   http://tug.ctan.org/tex-archive/info/svg-inkscape
+%%
+\begingroup%
+  \makeatletter%
+  \providecommand\color[2][]{%
+    \errmessage{(Inkscape) Color is used for the text in Inkscape, but the package 'color.sty' is not loaded}%
+    \renewcommand\color[2][]{}%
+  }%
+  \providecommand\transparent[1]{%
+    \errmessage{(Inkscape) Transparency is used (non-zero) for the text in Inkscape, but the package 'transparent.sty' is not loaded}%
+    \renewcommand\transparent[1]{}%
+  }%
+  \providecommand\rotatebox[2]{#2}%
+  \newcommand*\fsize{\dimexpr\f@size pt\relax}%
+  \newcommand*\lineheight[1]{\fontsize{\fsize}{#1\fsize}\selectfont}%
+  \ifx\svgwidth\undefined%
+    \setlength{\unitlength}{595.27559055bp}%
+    \ifx\svgscale\undefined%
+      \relax%
+    \else%
+      \setlength{\unitlength}{\unitlength * \real{\svgscale}}%
+    \fi%
+  \else%
+    \setlength{\unitlength}{\svgwidth}%
+  \fi%
+  \global\let\svgwidth\undefined%
+  \global\let\svgscale\undefined%
+  \makeatother%
+  \begin{picture}(1,1.41428571)%
+    \lineheight{1}%
+    \setlength\tabcolsep{0pt}%
+    \put(0,0){\includegraphics[width=\unitlength,page=1]{drawing_svg-tex.pdf}}%
+    \put(0.15789822,0.92036082){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}0x00\end{tabular}}}}%
+    \put(0.37386671,0.92253403){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}B1\end{tabular}}}}%
+    \put(0.50353176,0.92253403){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}B2\end{tabular}}}}%
+    \put(0.44040222,0.92253403){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}L1\end{tabular}}}}%
+    \put(0.61435089,0.92253403){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}L2\end{tabular}}}}%
+    \put(0.29055594,0.92253403){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}V1\end{tabular}}}}%
+    \put(0.66655026,0.92263452){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}V100\end{tabular}}}}%
+    \put(0,0){\includegraphics[width=\unitlength,page=2]{drawing_svg-tex.pdf}}%
+    \put(0.40749174,0.93578629){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}10\end{tabular}}}}%
+    \put(0.56205117,0.93578629){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}20\end{tabular}}}}%
+    \put(0.22755263,0.93517601){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}os\end{tabular}}}}%
+    \put(0.30978512,0.76763965){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}(V1,V100)\end{tabular}}}}%
+    \put(0.3264479,0.69374911){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}Range\end{tabular}}}}%
+    \put(0.20039115,0.69367397){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}Offset\end{tabular}}}}%
+    \put(0.2274294,0.76524569){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}os\end{tabular}}}}%
+    \put(0.22962278,0.7364222){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}...\end{tabular}}}}%
+    \put(0.35751119,0.7364222){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}...\end{tabular}}}}%
+    \put(0,0){\includegraphics[width=\unitlength,page=3]{drawing_svg-tex.pdf}}%
+    \put(0.52683919,0.82449268){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}\textbf{malloc}(..){\\  if (!set){\\    shm_largepage(1GB);\\  }\\  ...\\}  \end{tabular}}}}%
+    \put(0.25489157,0.65342298){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}L1 TLB\end{tabular}}}}%
+    \put(0,0){\includegraphics[width=\unitlength,page=4]{drawing_svg-tex.pdf}}%
+    \put(0.32993557,1.25595083){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}p\end{tabular}}}}%
+    \put(0.36330546,1.2544215){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}IE\end{tabular}}}}%
+    \put(0.3995023,1.25427548){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}s\end{tabular}}}}%
+    \put(0.46365018,1.2544215){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}L1\end{tabular}}}}%
+    \put(0.4283773,1.2544215){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}B1\end{tabular}}}}%
+    \put(0.36500369,1.2764865){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}Address\end{tabular}}}}%
+    \put(0,0){\includegraphics[width=\unitlength,page=5]{drawing_svg-tex.pdf}}%
+    \put(0.32168997,1.23225528){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}security data\end{tabular}}}}%
+    \put(0.4952568,1.25986266){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}Compressed\\Bounds\end{tabular}}}}%
+    \put(0.21413231,1.14693542){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}p\end{tabular}}}}%
+    \put(0.24752412,1.14540509){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}IE\end{tabular}}}}%
+    \put(0.28374472,1.14525897){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}s\end{tabular}}}}%
+    \put(0.34793472,1.14540509){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}L2\end{tabular}}}}%
+    \put(0.31263868,1.14540509){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}B2\end{tabular}}}}%
+    \put(0.24922346,1.16748457){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}Address\end{tabular}}}}%
+    \put(0,0){\includegraphics[width=\unitlength,page=6]{drawing_svg-tex.pdf}}%
+    \put(0.20495392,1.12507906){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}security data\end{tabular}}}}%
+    \put(0.18030792,1.3571531){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}main() {\end{tabular}}}}%
+    \put(0.18320669,1.0714103){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}}\end{tabular}}}}%
+    \put(0.20085456,1.31122079){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}\textbf{CapPtr} = malloc(10)\end{tabular}}}}%
+    \put(0.20671349,1.19496148){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}malloc(20)\end{tabular}}}}%
+    \put(0,0){\includegraphics[width=\unitlength,page=7]{drawing_svg-tex.pdf}}%
+    \put(0.46258094,1.31210798){\makebox(0,0)[lt]{\lineheight{1.25}\smash{\begin{tabular}[t]{l}Free(\textbf{CapPtr})\end{tabular}}}}%
+    \put(0,0){\includegraphics[width=\unitlength,page=8]{drawing_svg-tex.pdf}}%
+  \end{picture}%
+\endgroup%

docs/MeetingNotes/meeting-notes.org

@@ -0,0 +1,6 @@
+* Discussion
+- Upcoming conferences to submit the current paper in.
+- Timeline to send to Jeremy for a review and present a talk in Glasgow.
+- Discussion paper writing pipline plan (FAT allocator paper).
+- 2nd Expirement paper submission plan (To Submit by July in my Calendar).
+  

localpush.sh

@@ -2,5 +2,5 @@ files=`find . -newermt "-3600 secs" | sed 's|^./||'`
 
 for file in $files
 do
-       scp -P 45161 "$file" "akilan@217.76.63.222:/home/akilan/Alloc-Test/CHERI-Allocator/$file"
+       scp -P 37327 "$file" "akilan@217.76.63.222:/home/akilan/Alloc-Test/CHERI-Allocator/$file"
 done