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Akilan Selvacoumar
2025-04-11 16:31:47 +01:00
parent 3cc683534d
commit f35a58d96d
7 changed files with 190 additions and 175 deletions
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47
docs/EuroSys/Paper/paper.aux
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docs/EuroSys/Paper/paper.bbl
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@@ -58,11 +58,6 @@ Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, and Xu~Cheng.
tagged pointers.
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Gokul~B. Kandiraju and Anand Sivasubramaniam.
\newblock Characterizing the d-tlb behavior of spec cpu2000 benchmarks.
\newblock {\em SIGMETRICS Perform. Eval. Rev.}, 30(1):129–139, June 2002.
\bibitem{jemalloc}
{JEMALLOC}.

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docs/EuroSys/Paper/paper.blg
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@@ -355,8 +355,8 @@ memory allocations. The contributions for the following paper are as follows:
used to optimize memory allocation by encoding memory bounds directly within pointers, reducing TLB reliance
(section ~\ref{sec:128bitCompressedBounds}).
\item \textbf{Memory Allocation Algorithms}: Provides new algorithms for allocating and freeing
physically contiguous memory, integrating huge pages with CHERI's capability-based bounds for enhanced memory management
\item \textbf{Memory Allocation Algorithms}: Provides an algorithms for allocating, freeing
physically contiguous memory and integrating huge pages with CHERI's capability-based bounds for enhanced memory management
(section ~\ref{sec:MemoryAllocator}).
\end{itemize}
@@ -364,7 +364,7 @@ Through comprehensive evaluation, including micro and macro benchmarks, we demon
to reduce TLB misses by up to 90\%, yielding significant improvements in wall clock runtimes for memory-intensive
applications. While its impact on larger, computation-heavy workloads is less pronounced,
the proposed allocator shows strong potential for advancing memory management in scenarios requiring
high memory throughput and low translation overhead.
high memory throughput by reducing the address translation overhead.
\section{Related work}
\label{sec:org0e192da}
@@ -435,7 +435,7 @@ reducing the need for costly page table walks.
\subsection{CHERI}
\label{sec:orgbf2eaac}
CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional processor
CHERI extends conventional processor
Instruction-Set Architectures (ISAs) with architectural capabilities to enable fine-grained
memory protection and highly scalable software compartmentalization. CHERI is a hybrid
capability architecture that can combine capabilities with conventional MMU (Memory Management Unit) based systems.
@@ -454,8 +454,8 @@ and abstraction extensions for scalable software compartmentalization.
\section{Fat Address Translations}
\label{sec:FatPointerTranslations}
This section talks about how Fat-pointer Address Translations uses the CHERI architecture to
bring about block based allocations in physically contiguous memory. Fat-pointer Address Translations
This section talks about how Fat Address Translations(FAT) uses the CHERI architecture to
bring about block based allocations in physically contiguous memory. FAT
leverages techniques like FlexPointer~\cite{chen_flexpointer_2023} and Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to
achieve lesser pressure in the TLB. A key component
in this implementation is the use of range addresses with CHERI CC~\cite{woodruff_cheri_2019}.
@@ -492,9 +492,8 @@ in this implementation is the use of range addresses with CHERI CC~\cite{woodruf
% \end{minipage}
\end{figure*}
Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (malloc()) and a proposed Fat-pointer Address
Translation method. The standard approach involves a C program interacting with a custom allocator, utilizing 48-bit
free virtual addresses and a TLB walk (L1, L2, L3) to achieve non-contiguous allocation in physical memory.
Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (malloc()) and a proposed FAT method. The standard approach involves a C program interacting with a custom allocator, utilizing 48-bit
free virtual addresses and a TLB walk (L1, L2 and L3 cache) to achieve non-contiguous allocation in physical memory.
This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks.
In contrast, the Fat-pointer Address Translations method employs a custom allocator leveraging
physically contiguous memory by using CHERI to encode
@@ -525,7 +524,7 @@ bounds within the pointers and as show in the figure \ref{fig:HighOverviewArchit
% tracking of memory ranges on a pointer level.
A memory range in FAT has 2 points to track memory in physical contiguous space which
is the top and bottom. These 2 points are 2 virtual addresses and the range consists of
addresses which lie within this and constitutes as addresses allocated by invoking malloc.
addresses which lie within this and refers to addresses allocated by invoking malloc.
In FAT memory ranges are established using
bounds encoded within the pointer, adhering to CHERI CC~\cite{woodruff_cheri_2019}
as referred in section ~\ref{sec:128bitCompressedBounds}.
@@ -557,8 +556,9 @@ By using the CHERI bounds, this method maintains the contiguity of the allocated
We use CHERI CC~\cite{woodruff_cheri_2019} to track regions of memory in physically contiguous space.
CHERI CC consists of compressed bounds that represent a 128-bit pointer within a 64-bit virtual address
system. Our approach uses the work of CHERI CC by using a single cycle t0 decode bounds from the
capability register and the bounds which are decoded are repurposed for tracking memory regions.
system. Our approach uses the work of CHERI CC by using a single cycle to decode bounds from the
capability register and the bounds which are decoded are repurposed for tracking memory which is eagerly
allocated.
% Our approach utilizes a single-cycle encoding and decoding mechanism for efficiency. While CHERI
% CC was originally designed for memory protection, it can also be repurposed for tracking memory regions,
% eliminating the need for multiple TLB entries for each allocation.
@@ -591,32 +591,32 @@ malloc. Offering a more flexible alternative than fixed-size TLB entries.
\caption{Fat-pointer Address Translations using huge pages}
\label{fig:HugePages}
\end{figure}
To build up based on Section ~\ref{sec:RangeMemory} and ~\ref{sec:128bitCompressedBounds}
we are able to pre-allocate memory using Huge pages and are able to mark smaller allocations
using ranges by storing them as bounds within the pointer. Each of the memory ranges can be
called a block. Since we have numerous blocks inside a huge page we allow block based
To build up based on Section ~\ref{sec:RangeMemory} and ~\ref{sec:128bitCompressedBounds}.
We are able to pre-allocate memory using huge pages and are able to mark smaller allocations
using ranges by storing them as bounds within the pointer. Each of these memory ranges can be
called as a block. Since we have numerous blocks inside a huge page we allow block based
memory patters within physically contiguous memory. As demonstrated with the allocator
implementation in section ~\ref{sec:MemoryAllocator}.
Traditional address translation methods rely on hierarchical
structures to map virtual addresses to physical addresses.
This often requires multiple entries to handle different
memory segments, which increases overhead and adds complexity
to the translation process~\cite{TLBBehavoir}. In contrast, Our approach
simplifies this by using a single TLB
entry to translate multiple addresses within a contiguous memory
range. This reduces the number of TLB entries needed, making the
translation process more efficient and less complex.
%Traditional address translation methods rely on hierarchical
%structures to map virtual addresses to physical addresses.
%This often requires multiple entries to handle different
%memory segments, which increases overhead and adds complexity
%to the translation process~\cite{TLBBehavoir}. In contrast, FAT
%simplifies this by using a single TLB
%entry to translate multiple addresses within a contiguous memory
%range. This reduces the number of TLB entries needed, making the
%translation process more efficient and less complex.
By consolidating address translations into a single TLB entry,
the FAT Based Address cuts down on the overhead of managing many entries.
It also takes advantage of the bounds encoded within fat-pointers
to track and access memory.
%By consolidating address translations into a single TLB entry,
%the FAT cuts down on the overhead of managing many entries.
%It also takes advantage of the bounds encoded within fat-pointers
%to track and access memory.
% This streamlined (TODO)
% approach allows for precise and effective memory management,
% especially within large, contiguous memory regions like huge pages.
Overall, it simplifies memory operations while improving performance
and reduces TLB overhead by reducing TLB walks.
%Overall, it simplifies memory operations while improving performance
%and reduces TLB overhead by reducing TLB walks.
Figure \ref{fig:HugePages} illustrates a use-case of huge pages where the green
line represents a sample access to read within a contigous
@@ -628,7 +628,7 @@ on physically contigous memory.
\section{Memory allocator design}
\label{sec:MemoryAllocator}
This section presents a straightforward memory allocator designed and implemented based on the
principles outlined in our approach. The allocator consists of three core functions: InitAlloc,
principles outlined FAT ~\cite{sec:FatPointerTranslations}. The allocator consists of three core functions: InitAlloc,
malloc, and free. The InitAlloc function initializes the memory pool, setting up the necessary
data structures and metadata required for efficient memory management. The malloc function is
responsible for allocating a contiguous block of memory of a specified size, while the free
@@ -664,7 +664,7 @@ explicitly encoded in the address, enabling efficient monitoring and management
Furthermore, this design uses shared huge page TLB entries to map
and track memory addresses. By encoding bounds directly into the address, the algorithm ensures that memory
accesses remain within the allocated region, thereby enhancing safety and reducing the risk of out-of-bounds
accesses remain within the allocated region, thereby reducing the risk of out-of-bounds
errors. This use of FAT-pointers and shared TLB entries not only aligns with the principles of
efficient memory management but also demonstrates a practical usecase of huge pages in CHERI.
@@ -680,13 +680,13 @@ efficient memory management but also demonstrates a practical usecase of huge pa
\end{algorithm}
The memory deallocation (Algorithm \ref{alg:free}) mechanism in the proposed allocator is facilitated by the FAT-pointer structure
introduced in the malloc algorithm. When the free function is invoked, it utilizes the metadata
introduced in the malloc algorithm. When the free function is invoked, it uses the metadata
embedded within the FAT-pointer to determine the range and size of the allocated memory region.
Specifically, the start and end addresses encoded in the FAT-pointer provide the necessary information
to identify the exact memory block to be deallocated. This allows the allocator to precisely unmap
the corresponding memory region from the address space, ensuring efficient and accurate memory management.
Specifically, the start and end addresses encoded in FAT to provide the necessary information
to identify the exact memory block to be deallocated. This allows the allocator to unmap
the corresponding memory region from the address space.
By extracting the bounds and size directly from the FAT-pointer, the free function eliminates the need
By extracting the bounds and size directly from FAT, the free function eliminates the need
for additional metadata lookups or complex data structures.
% , streamlining the deallocation process.
% This approach not only enhances performance but also reduces the risk of memory leaks or fragmentation.
@@ -715,6 +715,7 @@ with page table management and enhances memory access efficiency, which is criti
applications and kernel-level operations.
\section{Evaluation}
\label{sec:Evaluation}
We conducted tests of the FAT Pointer-based range addresses against Jemalloc~\cite{jemalloc},
the default memory allocator for CHERIBSD~\cite{cheribsd}, to assess the performance improvements
enabled by a CHERI-based huge page-aware allocator. Specifically, we evaluated
@@ -727,32 +728,32 @@ detailed aspects of the allocator's behavior. Macro benchmarks, on the other han
encompass larger, real-world C programs, allowing us to assess the allocator's
performance in more practical, real-world scenarios.
The experiment setup section details the software stack used for evaluation. It includes
The experiment setup (section~\ref{sec:Experiment}) details the software stack used for evaluation. It includes
the specific configurations, compiler options, and system environment tailored
to benchmark the proposed allocator. This ensures consistency and repeatability
in our results, providing a solid foundation for meaningful comparisons.
We further elaborated on the two classes of benchmarks executed. Micro benchmarks
We further elaborated on the two classes of benchmarks executed. Micro benchmarks (section~\cite{sec:Micro}).
focused on particular allocation and deallocation patterns, such as sequential and
random memory accesses, to stress-test the allocator under controlled conditions.
Macro benchmarks involved real-world applications, offering insights into how
Macro benchmarks (section~\cite{sec:Macro}) involved real-world applications, offering insights into how
the allocator performs with complex memory allocation demands, large datasets,
and varying execution contexts.
The results section presents the outcomes of our benchmarks, highlighting key metrics
The results (section~\cite{sec:Results}) presents the outcomes of our benchmarks, highlighting key metrics
such as TLB miss rates, memory usage, and runtime performance. We observed that the
proposed allocator demonstrated significant improvements in reducing TLB misses,
leading to noticeable enhancements in runtime efficiency for both micro and macro
benchmarks. The behavior of specific allocation patterns and their impact on memory
performance is detailed, providing a nuanced understanding of the allocator's effectiveness.
Based on the evaluated results, the usability of the proposed allocator shows promise
for applications requiring optimized memory management and reduced overhead from TLB misses.
However, limitations were also identified, such as scenarios where the allocator's performance
gains were marginal or where it introduced additional complexity in memory management. These
limitations provide a roadmap for future optimizations and refinements of the allocator design.
%Based on the evaluated results (section~\cite{sec:Usability}), the usability of the proposed allocator shows promise
%for applications requiring optimized memory management and reduced overhead from TLB misses.
%However, limitations were also identified, such as scenarios where the allocator's performance
%gains were marginal or where it introduced additional complexity in memory management.
\subsection{Experiment setup}
\label{sec:Experiment}
The CHERI Morello~\cite{Morello} board was used to evaluate the proposed memory allocator.
Morello implements the ARM A76 with enhanced server-class memory, featuring a
quad-core ARM CPU with capability extensions. The L1 and L2 caches were modified
@@ -827,7 +828,7 @@ the proposed changes.
The benchmarks~\cite{Benchmark} are classified into 2 classes:
\subsubsection{Micro benchmark}
\label{sec:org41c278c}
\label{sec:Micro}
\begin{itemize}
\item GLIBC: The Glibc benchmark evaluates the performance of
malloc and free functions in single-threaded, multi-threaded,
@@ -844,7 +845,7 @@ The benchmarks~\cite{Benchmark} are classified into 2 classes:
\end{itemize}
\subsubsection{Macro benchmark}
\label{sec:org89020f2}
\label{sec:Macro}
\begin{itemize}
\item Kmeans: Kmeans implements a parallelized K-means clustering algorithm that
assigns data points to clusters based on proximity to centroids,
@@ -863,6 +864,7 @@ timing help measure system performance and ensure correctness.
\subsection{Results}
\label{sec:Results}
\begin{figure*}[h]
\includegraphics[width=.9\linewidth]{diagram/bargraph.png}
\caption{\label{fig:bargraph}Percentage difference between the modified memory allocator against the default system memory allocator}
@@ -875,15 +877,15 @@ patterns benefit from its design. The results align with expectations, showcasin
of its capability to handle memory more efficiently by leveraging huge pages.
\begin{itemize}
\item L1 DTLB reads: There was noticeable reduction of L1 DTLB reads for kmeans of about on average
4\% lesser and for Glibc there was significant reduction of 50\% than Jemalloc.
\item L1 DTLB reads: There was noticeable reduction of L1 DTLB reads for kmeans of about an average of
4\% lesser and for Glibc there was significant reduction of 50\% lesser than Jemalloc.
\item L2 DTLB reads: For all the benchmarks on figure \ref{fig:bargraph} there was on average 98\%
reduction on L2 DTLB reads. Which demonstrates that all TLB translations are read at the L1 TLB
reduction on L2 DTLB reads. This demonstrates that all the TLB translations are read at the L1 TLB
cache.
\item L1 DTLB walks: Due to most of the TLB entries getting hit at the L1TLB there is no need
to walk the TLB cache hierarchy. This is shown by on average 99\% reduction in DTLB walks.
\item L1 DTLB walks: Due to most of the TLB entries getting hit at the L1 DTLB there is no need
to walk the TLB cache hierarchy. This is shown by an average of 99\% reduction in DTLB walks.
\item L1 DTLB refills: Since there are lesser DTLB walks and most reads are done at the L1 DTLB
layer there is no need for numerous TLB refills to take place. Our benchmarks show on average
@@ -897,16 +899,16 @@ benchmarks compared to Jemalloc. This improvement is due to the modified allocat
use of a single huge page entry at the L1 TLB layer. By enabling most address translations
to be resolved directly at the L1 TLB, the need to walk through the deeper TLB hierarchy is
largely eliminated. This reduction in translation overhead is a key factor in the allocator's
superior performance for certain types of workloads.
performance for certain types of workloads.
The micro benchmarks, which are crafted to emphasize memory read operations, highlight the
allocator's strengths. These tests simulate frequent and intensive memory access patterns,
where the reduction in TLB misses directly translates into measurable performance gains.
On average, the FAT pointer allocator achieves a 50\% reduction in wall clock runtimes for
On average, the FAT allocator achieves a 50\% reduction in wall clock runtimes for
these workloads, underscoring its ability to optimize high-throughput memory operations.
On the other hand, macro benchmarks, which represent larger and more complex real-world applications,
exhibit minimal differences in wall clock runtimes when using the FAT pointer allocator.
exhibit minimal differences in wall clock runtimes when using the FAT allocator.
This outcome is expected, as macro benchmarks typically involve a broader range of operations
beyond memory allocation, diluting the impact of the allocator's optimizations. Additionally,
the benefits of huge pages may be less pronounced for these workloads, as they are often
@@ -932,7 +934,7 @@ the K-means algorithm.
However, an anomaly was observed at a cluster size of 2000, where the percentage difference
deviated significantly from the trend. At this cluster size, the memory access patterns and allocation behavior may align in a way that
temporarily offsets the advantages of the FAT pointer allocator. For example, the memory layout
temporarily offsets the advantages of the FAT allocator. For example, the memory layout
might interact with system-level caching mechanisms or TLB behavior differently, leading to an
unexpected change in performance. Additionally, the increased complexity of managing a higher
number of clusters might introduce computational overhead that overshadows the memory allocator's
@@ -945,8 +947,8 @@ behavior and guide future improvements to address such outliers. Despite the dev
cluster size of 2000, the overall results reaffirm the allocator's capability to maintain
consistent performance benefits across most scenarios.
\subsection{Usability}
\label{sec:orgd6ba6f0}
\subsection{Analysis}
\label{sec:Analysis}
The FAT pointer memory allocator demonstrates significant potential for enhancing
memory management in systems that benefit from huge page optimizations. Its design
effectively reduces TLB misses, achieving up to 90\% fewer data TLB walks, L2 TLB reads,