107 lines
5.4 KiB
Org Mode
107 lines
5.4 KiB
Org Mode
* Plan
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This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year.
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** Current experiments:
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1. FAT allocator with huge pages.
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2. FAT allocator to bypass TLB.
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3. Allocator evaluation based on stripping instruction calls for larger allocators.
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** Experiment cancelled:
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1. Uni-Kernel Development: Work scaled down to fit within the allocated PhD timeframe and introduced an extension of the FAT allocator as the third experiment.
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** Link to the Previous PhD Plan
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- https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf
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** Summary of the Previous Plan
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*** Phase 1: FAT-Pointer Mechanism (July–September 2024)
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**** 1st to 15th July 2024
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- Investigated causes of L1 TLB misses associated with contiguous memory allocation.
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- Executed performance benchmarking using COZ on selected C programs.
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- Ported the kernel module to support SnMalloc, the default allocator in CheriBSD.
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**** 15th to 30th July 2024
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- Conducted benchmarking using the SPEC and XSBench suites.
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- Performed comparative analysis with both baseline and modified SnMalloc implementations.
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**** August 2024
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- Initiated drafting of a paper for submission to EuroSys, focusing on the FAT-Pointer memory allocator.
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**** September 2024
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- Compiled and structured thesis chapter related to the FAT-Pointer architecture.
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- Finalised and submitted the EuroSys paper.
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*** Phase 2: RISC-V Integration (October 2024 – May 2025)
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**** October to December 2024
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- Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline.
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- Configured the experimental platform and evaluation toolchain.
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**** January to February 2025
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- Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba).
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- Commenced drafting of a technical paper for ISMM based on RISC-V integration results.
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**** March to May 2025
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- Addressed outstanding tasks and technical backlog.
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- Continued development of the corresponding thesis chapter.
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*** Phase 3: Uni-Kernel Deployment (May 2025 – September 2026)
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**** May to December 2025
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- Ported the memory allocator to a CHERI-enabled Uni-Kernel environment.
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- Designed and implemented a unified memory allocator to support both kernel and user-level allocations.
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- Initiated drafting of a manuscript targeted at OSDI.
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**** January to September 2026
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- Finalised documentation and submission of the PhD thesis.
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- Submitted third research paper based on extended evaluation.
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** Current Research Plan
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This section outlines a comprehensive timeline of research activities and academic milestones undertaken between June
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2025 and September 2026 as part of the PhD focused on the CHERI Toooba architecture. It includes the refactoring of BlueSpec SystemVerilog modules and the development of a bare-metal
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C benchmark suite. The work involves in-depth
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debugging of the Toooba memory subsystem, the design and evaluation of in-depth analyses of the FAT allocator and performance analysis at the instruction
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level. Alongside these technical efforts, the timeline reflects the structured drafting of academic publications and the ongoing development
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of the PhD thesis leading to the final submission of the dissertation.
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[[./gnatt-chart.png]]
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*** June to July 2025
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- Refactored BlueSpec SystemVerilog (BSV) modules within the CHERI Toooba architecture.
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- Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform.
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- Incorporated supervisory team feedback into revisions of the EuroSys paper.
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- Undertook formal progression review requirements.
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- Submitted EuroSys manuscript to the CHERI research team at the University of Glasgow for preliminary feedback.
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*** July to August 2025
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- Engaged in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path.
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- Finalised and validated the C benchmark suite for Toooba evaluation.
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- Began technical documentation of the Toooba workflow, to support a second publication.
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- Concluded revisions to the EuroSys paper by the end of July.
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*** August to September 2025
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- Continued debugging efforts within the Toooba memory subsystem.
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- Drafted the abstract, introduction, and methodology sections of the second research paper.
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- Aimed to generate preliminary experimental results for inclusion in the evaluation.
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*** September to October 2025
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- Published the EuroSys paper detailing the FAT-Pointer allocator.
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- Commenced benchmarking of the Toooba design.
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- Simultaneously drafted the evaluation and analysis sections of the second manuscript.
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*** October to November 2025
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- Initiated third experimental phase, aimed at deeper evaluation of prior experiments.
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- Modified memory allocators (TcMalloc and Mesh) to remove reliance on `mmap`.
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*** November to December 2025
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- Finalised second paper for peer review.
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- Stripped away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh.
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- Analysed instruction-level reductions and performance implications.
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- Commenced drafting of the third research paper, building on contributions from the EuroSys paper.
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*** December 2025 to January 2026
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- Conducted evaluation and profiling for the third paper.
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- Commenced thesis chapter write-up for Experiments 1 and 2.
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*** January to September 2026
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- Continued thesis development and refinement across all experimental chapters.
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- Finalised and submitted third paper for peer review.
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- Prepared complete PhD dissertation for submission.
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