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Hopefully don't wedge on ifetch bus error.

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We think that we were wedging on IFetch bus error.
It appears that we didn't make the last instruction fragment valid in the bus error case, and expect that this path was not previously exercised.
This change returns 0s (to hopefully make the error less subtle) in exactly the right number of fragments.
This commit is contained in:
Jonathan Woodruff
2021-09-08 10:11:25 -05:00
committed by GitHub
parent 0970951184
commit 08231b7e5c
1 changed files with 2 additions and 4 deletions
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6
src_Core/CPU/MMIOPlatform.bsv
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@@ -968,10 +968,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
// Access fault
Vector #(SupSizeX2, Maybe #(Instruction16)) resp = replicate (Invalid);
for(Integer i = 0; i < valueof (SupSizeX2); i = i+1) begin
if (fromInteger (i) < fetchingWay)
resp [i] = Valid (fetchedInsts [i]);
else if (fromInteger (i) == fetchingWay)
resp [i] = tagged Invalid;
if (fromInteger (i) <= fetchingWay)
resp [i] = Valid (unpack(pack(0)));
end
cores[reqCore].pRs.enq (tagged InstFetch resp);
state <= SelectReq;