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Reduce bit storage for stride prefetcher

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This commit is contained in:
Karlis Susters
2023-04-13 18:27:28 +03:00
parent 2ec0f37bbd
commit 2f428a974a
1 changed files with 3 additions and 3 deletions
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6
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
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@@ -1358,7 +1358,7 @@ typedef enum {
typedef struct {
Bit#(12) lastAddr;
Bit#(13) stride;
Bit#(4) cLinesPrefetched; //Stores how many cache lines have been prefetched for this instruction
Bit#(2) cLinesPrefetched; //Stores how many cache lines have been prefetched for this instruction
StrideState2 state;
} StrideEntry2 deriving (Bits, Eq, FShow);
@@ -1374,7 +1374,7 @@ provisos(
Fifo#(8, Addr) addrToPrefetch <- mkOverflowPipelineFifo;
FIFO#(Tuple3#(StrideEntry2, Addr, Bit#(16))) strideEntryForPrefetch <- mkBypassFIFO();
Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(?);
Reg#(Maybe#(Bit#(2))) cLinesPrefetchedLatest <- mkReg(?);
PulseWire holdReadReq <- mkPulseWire;
rule sendReadReq if (!holdReadReq);
@@ -1467,7 +1467,7 @@ provisos(
rule createPrefetchRequests;
match {.se, .addr, .pcHash} = strideEntryForPrefetch.first;
//If this rule is looping, then we'll have a valid cLinesPrefetchedLatest
Bit#(4) cLinesPrefetched = fromMaybe(se.cLinesPrefetched, cLinesPrefetchedLatest);
Bit#(2) cLinesPrefetched = fromMaybe(se.cLinesPrefetched, cLinesPrefetchedLatest);
if (se.state == STEADY &&
cLinesPrefetched !=