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Merge pull request #6 from nirajnsharma/master

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src_SSITH_P3 Makefile edits
This commit is contained in:
Rishiyur S. Nikhil
2020-01-03 04:37:48 -08:00
committed by GitHub
parent afce8b4a6d 364b1d1cf3
commit 35e0b09202
2 changed files with 13 additions and 3 deletions
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6
src_SSITH_P3/Makefile
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@@ -38,7 +38,11 @@ BSC_COMPILATION_FLAGS += \
#================================================================
# Parameter settings for MIT RISCY
# We omit 'BSC_COMPILATION_FLAGS += D BSIM' so it'll use Xilinx IP for floating point arith
# We include 'BSC_COMPILATION_FLAGS += D BSIM' to use simulation
# models for the integer divier. Omit this for synthesis.
ifeq ($(SIM), true)
BSC_COMPILATION_FLAGS += -D BSIM
endif
include $(REPO)/builds/Resources/Include_RISCY_Config.mk

10
src_SSITH_P3/README.txt
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@@ -29,9 +29,15 @@ into this socket:
- Variations/alternatives by various SSITH project teams
>================================================================
Whenever there are changes to the Piccolo core, rerun:
Whenever there are changes to the Toooba core, rerun:
$ make compile
$ make compile SIM=true for a simulation version
(which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)
$ make compile for a synthesizable (on Xilinx) version
(which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)
The simulation version uses simulation models for the integer divider,
while the synthesis version uses Xilinx IP.
>================================================================