Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

For src_SSITH_P3 builds, added conditions to include/exclude

Browse Source 
simulation models of the integer divider
This commit is contained in:
Niraj Nayan Sharma
2020-01-03 16:59:34 +05:30
parent afce8b4a6d
commit 364b1d1cf3
2 changed files with 13 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src_SSITH_P3/Makefile
View File

@@ -38,7 +38,11 @@ BSC_COMPILATION_FLAGS += \
#================================================================
# Parameter settings for MIT RISCY
# We omit 'BSC_COMPILATION_FLAGS += D BSIM' so it'll use Xilinx IP for floating point arith
# We include 'BSC_COMPILATION_FLAGS += D BSIM' to use simulation
# models for the integer divier. Omit this for synthesis.
ifeq ($(SIM), true)
BSC_COMPILATION_FLAGS += -D BSIM
endif
include $(REPO)/builds/Resources/Include_RISCY_Config.mk

10
src_SSITH_P3/README.txt
View File

@@ -29,9 +29,15 @@ into this socket:
- Variations/alternatives by various SSITH project teams
>================================================================
Whenever there are changes to the Piccolo core, rerun:
Whenever there are changes to the Toooba core, rerun:
$ make compile
$ make compile SIM=true for a simulation version
(which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)
$ make compile for a synthesizable (on Xilinx) version
(which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)
The simulation version uses simulation models for the integer divider,
while the synthesis version uses Xilinx IP.
>================================================================