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For src_SSITH_P3 builds, added conditions to include/exclude

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simulation models of the integer divider
This commit is contained in:
Niraj Nayan Sharma
2020-01-03 16:59:34 +05:30
parent afce8b4a6d
commit 364b1d1cf3
2 changed files with 13 additions and 3 deletions
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src_SSITH_P3/Makefile
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@@ -38,7 +38,11 @@ BSC_COMPILATION_FLAGS += \
#================================================================
# Parameter settings for MIT RISCY
# We omit 'BSC_COMPILATION_FLAGS += D BSIM' so it'll use Xilinx IP for floating point arith
# We include 'BSC_COMPILATION_FLAGS += D BSIM' to use simulation
# models for the integer divier. Omit this for synthesis.
ifeq ($(SIM), true)
BSC_COMPILATION_FLAGS += -D BSIM
endif
include $(REPO)/builds/Resources/Include_RISCY_Config.mk