Cheri-research/Toooba
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Remove some verbosity from the committed state.

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Jonathan Woodruff
2021-10-07 16:30:32 +00:00
parent 81a12b89cb
commit 3d0aee0af4
2 changed files with 3 additions and 3 deletions
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4
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -226,7 +226,7 @@ interface AluExePipeline;
endinterface
module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
Bool verbose = True;
Bool verbose = False;
Integer verbosity = 0;
// alu reservation station
@@ -323,7 +323,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
end
end
else if(x.dInst.iType == CJALR || x.dInst.iType == Jr) begin
let res_targets = inIfc.checkTarget(ppc);

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -252,7 +252,7 @@ interface MemExePipeline;
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
Bool verbose = True;
Bool verbose = False;
// we change cache request in case of single core, becaues our MSI protocol
// is not good with single core