Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models

src_SSITH_P3/Makefile

@@ -37,6 +37,7 @@ BSC_COMPILATION_FLAGS += \
 
 #================================================================
 # Parameter settings for MIT RISCY
+# We omit 'BSC_COMPILATION_FLAGS += D BSIM' so it'll use Xilinx IP for floating point arith
 
 include $(REPO)/builds/Resources/Include_RISCY_Config.mk