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Config for L1I MultiWindowTarget-2

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This commit is contained in:
Karlis Susters
2023-04-19 14:22:01 +03:00
parent cc65297cf9
commit 4bc04b581d
2 changed files with 5 additions and 5 deletions
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6
builds/Resources/Include_RISCY_Config.mk
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@@ -45,10 +45,10 @@ SIM_LLC_ARBITER_LAT ?=
# default check cache deadlock and rename error
CHECK_DEADLOCK ?= true
RENAME_DEBUG ?= false
INSTR_PREFETCHER_LOCATION ?= NONE
INSTR_PREFETCHER_TYPE ?= MULTI_WINDOW
INSTR_PREFETCHER_LOCATION ?= L1
INSTR_PREFETCHER_TYPE ?= MULTI_WINDOW_TARGET
DATA_PREFETCHER_LOCATION ?= NONE
DATA_PREFETCHER_TYPE ?= STRIDE
DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT_2
# clk frequency depends on core size
ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))

4
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
View File

@@ -816,14 +816,14 @@ provisos(
Vector#(numWindows, Reg#(windowIdxT)) shiftReg <- genWithM(compose(mkReg, fromInteger));
Reg#(LineAddr) lastChildRequest <- mkReg(0);
TargetTableBRAM#(64, 8) targetTable <- mkTargetTableBRAM;
TargetTableBRAM#(8192, 2048) targetTable <- mkTargetTableBRAM;
FIFOF#(LineAddr) targetTableReadResp <- mkBypassFIFOF;
Reg#(Vector#(numLastRequests, Bit#(32))) lastTargetRequests <- mkReg(replicate(0));
rule sendReadReq;
if (!elem(hash(lastChildRequest), lastTargetRequests)) begin
targetTable.readReq(lastChildRequest);
$display("%t Prefetcher sending target read request for %h", $time, lastChildRequest);
$display("%t Prefetcher sending target read request for %h", $time, Addr'{lastChildRequest, 'h0});
lastTargetRequests <= shiftInAt0(lastTargetRequests, hash(lastChildRequest));
end
endrule