Bugfix for L1LL D prefetchers, config for L1LL D Stride-3

2023-03-08 13:37:04 +00:00
parent 30a3aff5af
commit 54b9f6669e
2 changed files with 2 additions and 2 deletions
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -47,7 +47,7 @@ CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
 INSTR_PREFETCHER_LOCATION ?= NONE
 INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW
-DATA_PREFETCHER_LOCATION ?= L1
+DATA_PREFETCHER_LOCATION ?= L1LL
 DATA_PREFETCHER_TYPE ?= STRIDE

 # clk frequency depends on core size
--- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
@@ -498,7 +498,7 @@ endfunction
        cRqToPT cRqToP = CRqMsg {
            addr: addr,
            fromState: ?,
-            toState: M,
+            toState: S,
            canUpToE: True,
            id: 0,
            child: ?,