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iMove the store count to the pipeline write.

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It appeared to be counting capabilities in store counter flushes, which,
FI think, is not quite what was intended in this counter.
This commit is contained in:
jon
2020-12-11 17:16:38 +00:00
parent 19a07882ab
commit 6768bf92c7
1 changed files with 6 additions and 2 deletions
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8
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -276,7 +276,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`endif
`ifdef PERFORMANCE_MONITORING
Array #(Wire #(EventsCoreMem)) events_wire <- mkDWireOR (4, unpack (0));
Array #(Wire #(EventsCoreMem)) events_wire <- mkDWireOR (5, unpack (0));
Reg #(EventsCoreMem) events_reg <- mkReg(unpack(0));
rule update_events_reg;
events_reg <= events_wire[0];
@@ -381,7 +381,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
EventsCoreMem events = unpack(0);
if (waitSt.shiftedBE == -1) events.evt_MEM_CAP_STORE = 1;
events.evt_STORE_WAIT = saturating_truncate(lat);
events.evt_MEM_CAP_STORE_TAG_SET = (waitSt.shiftedData.tag) ? 1 : 0;
events_wire[2] <= events;
`endif
// now figure out the data to be written
@@ -547,6 +546,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(x.ldstq_tag matches tagged St .stTag) begin
MemTaggedData d = x.mem_func == Amo ? toMemData : shiftData; // XXX don't shift for AMO
lsq.updateData(stTag, d);
`ifdef PERFORMANCE_MONITORING
EventsCoreMem events = unpack(0);
events.evt_MEM_CAP_STORE_TAG_SET = (d.tag) ? 1 : 0;
events_wire[4] <= events;
`endif
end
CapPipe ddc = cast(inIfc.scaprf_rd(scrAddrDDC));