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Extend the final missed id width

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Peter Rugg
2023-02-10 17:09:20 +00:00
parent b0316afcb7
commit 69b96cc68f
1 changed files with 1 additions and 1 deletions
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src_SSITH_P3/xilinx_ip/component.xml
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@@ -1047,7 +1047,7 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">5</spirit:left>
<spirit:left spirit:format="long">6</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>