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Rename 'cap-mode' in Mem pipeline to ddc offset, since explicit memory instructions contradicting the cap_mode exist

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This commit is contained in:
Peter Rugg
2020-05-29 17:05:03 +01:00
parent a7d4d8e4a4
commit 6a8f0e5bc0
3 changed files with 6 additions and 6 deletions
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6
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -64,7 +64,7 @@ typedef struct {
InstTag tag;
LdStQTag ldstq_tag;
CapChecks cap_checks;
Bool cap_mode;
Bool ddc_offset;
} MemDispatchToRegRead deriving(Bits, Eq, FShow);
typedef struct {
@@ -402,7 +402,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
tag: x.tag,
ldstq_tag: x.data.ldstq_tag,
cap_checks: x.data.cap_checks,
cap_mode: x.data.cap_mode
ddc_offset: x.data.ddc_offset
},
spec_bits: x.spec_bits
});
@@ -431,7 +431,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
end
if (!x.cap_mode) rVal1 = nullWithAddr(getAddr(rVal1) + getAddr(ddc));
if (x.ddc_offset) rVal1 = nullWithAddr(getAddr(rVal1) + getAddr(ddc));
// get rVal2 (check bypass)
CapPipe rVal2 = nullCap;

4
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
View File

@@ -677,7 +677,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
imm: validValue(dInst.imm),
ldstq_tag: lsqTag,
cap_checks: dInst.capChecks,
cap_mode: dInst.execFunc.Mem.reg_bounds
ddc_offset: !dInst.execFunc.Mem.reg_bounds
},
regs: phy_regs,
tag: inst_tag,
@@ -1017,7 +1017,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
imm: validValue(dInst.imm),
ldstq_tag: lsqTag,
cap_checks: dInst.capChecks,
cap_mode: dInst.execFunc.Mem.reg_bounds
ddc_offset: !dInst.execFunc.Mem.reg_bounds
},
regs: phy_regs,
tag: inst_tag,

2
src_Core/RISCY_OOO/procs/RV64G_OOO/ReservationStationMem.bsv
View File

@@ -32,7 +32,7 @@ typedef struct {
ImmData imm;
LdStQTag ldstq_tag;
CapChecks cap_checks;
Bool cap_mode;
Bool ddc_offset;
} MemRSData deriving(Bits, Eq, FShow);
// MEM pipeline is aggressive, i.e. it recv bypass and early RS wakeup