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Don't push capabilities into FpuMulDivExePipeline

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We needlessly casted to CapPipe then FpuMulDivExePipeline had to
internally get the address and construct null-derived capabilities. Push
all this out to the Core so that it just deals with Data again. This is
unlikely to affect area as any sane optimiser would have optimised all
this away, but this is cleaner code, with the benefit that the FPU no
longer cares if the physical register file is unified or split between
GPCRs and FPRs.
This commit is contained in:
Jessica Clarke
2020-07-13 15:52:27 +01:00
parent 4792581d8c
commit 6d4b00c865
2 changed files with 13 additions and 13 deletions
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10
src_Core/CPU/Core.bsv
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@@ -422,15 +422,15 @@ module mkCore#(CoreId coreId)(Core);
for(Integer i = 0; i < valueof(FpuMulDivExeNum); i = i+1) begin
let fpuMulDivExeInput = (interface FpuMulDivExeInput;
method sbCons_lazyLookup = sbCons.lazyLookup[fpuMulDivRdPort(i)].get;
method rf_rd1 = cast(rf.read[fpuMulDivRdPort(i)].rd1);
method rf_rd2 = cast(rf.read[fpuMulDivRdPort(i)].rd2);
method rf_rd3 = cast(rf.read[fpuMulDivRdPort(i)].rd3);
method rf_rd1 = compose(getAddr, rf.read[fpuMulDivRdPort(i)].rd1);
method rf_rd2 = compose(getAddr, rf.read[fpuMulDivRdPort(i)].rd2);
method rf_rd3 = compose(getAddr, rf.read[fpuMulDivRdPort(i)].rd3);
method csrf_rd = csrf.rd;
method scaprf_rd = csrf.scrRd;
method rob_setExecuted = rob.setExecuted_doFinishFpuMulDiv[i].set;
method Action writeRegFile(PhyRIndx dst, CapPipe data);
method Action writeRegFile(PhyRIndx dst, Data data);
writeAggr(fpuMulDivWrAggrPort(i), dst);
writeCons(fpuMulDivWrConsPort(i), dst, data);
writeCons(fpuMulDivWrConsPort(i), dst, nullWithAddr(data));
endmethod
method conflictWrongSpec = globalSpecUpdate.conflictWrongSpec[finishFpuMulDivConflictWrongSpecPort(i)].put(?);
method doStats = doStatsReg._read;

16
src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
View File

@@ -101,9 +101,9 @@ interface FpuMulDivExeInput;
// conservative scoreboard check in reg read stage
method RegsReady sbCons_lazyLookup(PhyRegs r);
// Phys reg file
method CapPipe rf_rd1(PhyRIndx rindx);
method CapPipe rf_rd2(PhyRIndx rindx);
method CapPipe rf_rd3(PhyRIndx rindx);
method Data rf_rd1(PhyRIndx rindx);
method Data rf_rd2(PhyRIndx rindx);
method Data rf_rd3(PhyRIndx rindx);
// CSR file
method Data csrf_rd(CSR csr);
// Special Capability Register file.
@@ -123,7 +123,7 @@ interface FpuMulDivExeInput;
// global broadcast methods
// write reg file & set both conservative and aggressive sb & wake up inst
method Action writeRegFile(PhyRIndx dst, CapPipe data);
method Action writeRegFile(PhyRIndx dst, Data data);
// spec update
method Action conflictWrongSpec;
// performance
@@ -196,19 +196,19 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
// get rVal1 (check bypass)
Data rVal1 = ?;
if(x.regs.src1 matches tagged Valid .src1) begin
rVal1 <- readRFBypass(src1, regsReady.src1, getAddr(inIfc.rf_rd1(src1)), bypassWire);
rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
end
// get rVal2 (check bypass)
Data rVal2 = ?;
if(x.regs.src2 matches tagged Valid .src2) begin
rVal2 <- readRFBypass(src2, regsReady.src2, getAddr(inIfc.rf_rd2(src2)), bypassWire);
rVal2 <- readRFBypass(src2, regsReady.src2, inIfc.rf_rd2(src2), bypassWire);
end
// get rVal3 (check bypass)
Data rVal3 = ?;
if(x.regs.src3 matches tagged Valid .src3) begin
rVal3 <- readRFBypass(src3, regsReady.src3, getAddr(inIfc.rf_rd3(src3)), bypassWire);
rVal3 <- readRFBypass(src3, regsReady.src3, inIfc.rf_rd3(src3), bypassWire);
end
// go to next stage
@@ -253,7 +253,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
action
// write to register file
if(dst matches tagged Valid .valid_dst) begin
inIfc.writeRegFile(valid_dst.indx, nullWithAddr(data));
inIfc.writeRegFile(valid_dst.indx, data);
end
// update the instruction in the reorder buffer.
inIfc.rob_setExecuted(tag,