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Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction

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This commit is contained in:
Jonathan Woodruff
2022-03-25 13:06:22 +00:00
parent ad7bcbb559 d0c1d97a2a
commit 6d7f95571f
17 changed files with 42 additions and 26 deletions
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5
builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
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@@ -3,6 +3,11 @@
REPO ?= ../..
ARCH ?= RV64ACDFIMSUxCHERI
# ================================================================
# Path to RISCY-OOO sources not included in Common
EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/BSV-RVFI-DII
# ================================================================
# RISC-V config macros passed into Bluespec 'bsc' compiler

2
builds/Resources/Include_bluesim.mk
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@@ -15,6 +15,8 @@ build_dir:
ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
include .depends.mk
BSC_COMPILATION_FLAGS += -D RVFI
.depends.mk: TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv | build_dir
if ! bluetcl -exec makedepend -elab -sim $(TMP_DIRS) $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
endif

2
libs/BlueStuff

Submodule libs/BlueStuff updated: a6e2273920...8a36aa9af4

2
libs/TagController

Submodule libs/TagController updated: 99c43e8138...2e2198b05f

12
src_Core/CPU/Core.bsv
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@@ -748,7 +748,17 @@ module mkCore#(CoreId coreId)(Core);
CommitStage commitStage <- mkCommitStage(commitInput);
`ifdef RVFI
mkConnection(commitStage.rvfi, rvfi_bridge.rvfi);
// XXX Currently RVFI can only be connected to the outside world
// via the RVFI_DII bridge i.e. when DII is also being used.
rule drop;
let packets <- commitStage.rvfi.get();
for (Integer i = 0; i < valueOf(SupSize); i = i+1) begin
if (isValid(packets[i])) $display("%d: RVFI ", cur_cycle, fshow(packets[i].Valid));
end
`ifdef RVFI_DII
rvfi_bridge.rvfi.put(packets);
`endif
endrule
`endif
// send rob enq time to reservation stations

2
src_Core/CPU/MMIO_AXI4_Adapter.bsv
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@@ -76,7 +76,7 @@ endinterface
module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// Verbosity: 0: quiet; 1: transactions
Integer verbosity = 1;
Integer verbosity = 0;
Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
// ================================================================

5
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -506,8 +506,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
isCompressed: x.isCompressed},
spec_bits: train_spec_bits
});
$display("alu mispredict pc¤: %x, nextPc: %x, %d",
x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle);
if (verbose)
$display("alu mispredict pc: %x, nextPc: %x, %d",
x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle);
`ifdef PERF_COUNT
// performance counter
if(inIfc.doStats) begin

6
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -200,7 +200,7 @@ typedef struct {
Addr addr;
Trap trap;
Bit #(32) orig_inst;
`ifdef RVFI_DII
`ifdef RVFI
ToReorderBuffer x;
`endif
} CommitTrap deriving(Bits, FShow);
@@ -290,7 +290,7 @@ deriving (Eq, FShow, Bits);
module mkCommitStage#(CommitInput inIfc)(CommitStage);
Bool verbose = False;
Integer verbosity = 1; // Bluespec: for lightweight verbosity trace
Integer verbosity = 0; // Bluespec: for lightweight verbosity trace
// Used to inform tandem-verifier about program order.
// 0 is used to indicate we've just come out of reset
@@ -688,7 +688,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
pc: x.pc,
addr: vaddr,
orig_inst: x.orig_inst
`ifdef RVFI_DII
`ifdef RVFI
, x: x
`endif
});

2
src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
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@@ -260,7 +260,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
data,
`endif
fflags
`ifdef RVFI_DII
`ifdef RVFI
, ExtraTraceBundle{regWriteData: data, memByteEn: ?}
`endif
);

6
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -523,7 +523,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
});
endrule
`ifdef RVFI_DII
`ifdef RVFI
Vector#(TExp#(SizeOf#(LdStQTag)), Reg#(Data)) memData <- replicateM(mkReg(?));
`endif
@@ -538,9 +538,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
CapPipe data = x.rVal2;
MemTaggedData toMemData = unpack(pack(toMem(data)));
`ifdef RVFI_DII
`ifdef RVFI
memData[pack(x.ldstq_tag)] <= getAddr(data);
$display("%t : memData[%x] <= %x", $time(), pack(x.ldstq_tag), getAddr(data));
`endif
// get shifted data and BE
@@ -856,7 +855,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`ifdef RVFI
LdStQTag idx = tagged Ld tag;
memData[pack(idx)] <= truncate(pack(res.data)); // TODO use fromMem?
$display("%t : memData[%x] <= %x", $time(), pack(idx), res.data);
`endif
end
if(res.wrongPath) begin

2
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
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@@ -732,7 +732,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
doAssert((dInst.iType != Fence) == isValid(dInst.imm),
"Mem (non-Fence) needs imm for virtual addr");
Bit#(16) dum = hash(getAddr(pc));
$display("pc : %x , hash(pc) : %x", pc, dum);
// put in ldstq
if(isLdQ) begin
lsq.enqLd(inst_tag, mem_inst, allow_cap, phy_regs.dst, spec_bits, hash(getAddr(pc)));
@@ -1073,7 +1072,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
doAssert(!isValid(spec_tag), "should not have spec tag");
// put in ldstq
Bit#(16) dum = hash(getAddr(pc));
$display("pc : %x , hash(pc) : %x", pc, dum);
if(isLdQ) begin
lsq.enqLd(inst_tag, mem_inst, phy_regs.dst, spec_bits, hash(getAddr(pc)));
end

9
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
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@@ -287,10 +287,11 @@ module mkDTlb#(
end
else if(pRs.entry matches tagged Valid .en) begin
// check permission
$display("dPRs: vm_info: ", fshow(vm_info),
" en : ", fshow(en),
" r : ", fshow(r)
);
if (verbose)
$display("dPRs: vm_info: ", fshow(vm_info),
" en : ", fshow(en),
" r : ", fshow(r)
);
let permCheck = hasVMPermission(vm_info,
en.pteType,
en.pteUpperType,

6
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -46,7 +46,7 @@ import MemoryTypes::*;
import CHERICap::*;
import CHERICC_Fat::*;
import ISA_Decls_CHERI::*;
`ifdef RVFI_DII
`ifdef RVFI
import GetPut::*;
import RVFI_DII_Types::*;
`endif
@@ -86,8 +86,10 @@ typedef struct {
`endif
} InstTag deriving(Bits, Eq, FShow);
`ifdef RVFI_DII
`ifdef RVFI
typedef Vector#(SupSize, Maybe#(RVFI_DII_Execution #(64, 64))) Rvfi_Traces;
`endif
`ifdef RVFI_DII
typedef Vector#(TMul#(SupSize, 2), RVFI_DII_Parcel_Resp) Dii_Parcel_Resps;
typedef Vector#(TMul#(SupSize, 2), Bit#(16)) Dii_Parcels;

1
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
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@@ -756,7 +756,6 @@ module mkSupReorderBuffer#(
// move deqP & reset valid
deqP[i] <= getNextPtr(deqP[i]);
valid[i][deqP[i]][valid_deq_port] <= False;
$display("deq[%d][%d]", i, deqP[i]);
end
end
// update firstDeqWay: find the first deq port that is not enabled

2
src_Testbench/SoC/SoC_Top.bsv
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@@ -209,7 +209,7 @@ module mkSoC_Top #(Reset dm_power_on_reset)
`ifdef INCLUDE_ACCEL0
// Fabric to accel0
slave_vector[accel0_slave_num] = zeroSlaveUserFields (accel0.slave);
slave_vector[accel0_slave_num] = zero_AXI4_Slave_user(accel0.slave);
route_vector[accel0_slave_num] = soc_map.m_accel0_addr_range;
`endif

2
src_Testbench/Top/Mem_Model.bsv
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@@ -81,7 +81,7 @@ typedef Bit#(TSub#(TSub#(TLog#(TSub#(Zeroed_1_end, Zeroed_1_start)), LogZMWidth)
(* synthesize *)
module mkMem_Model (Mem_Model_IFC);
Integer verbosity = 1; // 0 = quiet; 1 = verbose
Integer verbosity = 0; // 0 = quiet; 1 = verbose
Raw_Mem_Addr alloc_size = fromInteger(valueOf(TDiv#(TMul#(Bytes_Per_Mem,8), Bits_per_Raw_Mem_Word))); //(raw mem words)

2
src_Verifier/BSV-RVFI-DII

Submodule src_Verifier/BSV-RVFI-DII updated: 8a15990997...b6aa39d1c3