Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction

src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv

@@ -506,8 +506,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
                     isCompressed: x.isCompressed},
                 spec_bits: train_spec_bits
             });
-            $display("alu mispredict pc¤: %x, nextPc: %x, %d",
-                     x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle);
+            if (verbose)
+                $display("alu mispredict pc: %x, nextPc: %x, %d",
+                         x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle);
 `ifdef PERF_COUNT
             // performance counter
             if(inIfc.doStats) begin

src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv

@@ -200,7 +200,7 @@ typedef struct {
     Addr addr;
     Trap trap;
     Bit #(32) orig_inst;
-`ifdef RVFI_DII
+`ifdef RVFI
     ToReorderBuffer x;
 `endif
 } CommitTrap deriving(Bits, FShow);
@@ -290,7 +290,7 @@ deriving (Eq, FShow, Bits);
 module mkCommitStage#(CommitInput inIfc)(CommitStage);
     Bool verbose = False;
 
-    Integer verbosity = 1;   // Bluespec: for lightweight verbosity trace
+    Integer verbosity = 0;   // Bluespec: for lightweight verbosity trace
 
     // Used to inform tandem-verifier about program order.
     // 0 is used to indicate we've just come out of reset
@@ -688,7 +688,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
             pc: x.pc,
             addr: vaddr,
             orig_inst: x.orig_inst
-`ifdef RVFI_DII
+`ifdef RVFI
             , x: x
 `endif
         });

src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv

@@ -260,7 +260,7 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
                               data,
 `endif
                               fflags
-`ifdef RVFI_DII
+`ifdef RVFI
                               , ExtraTraceBundle{regWriteData: data, memByteEn: ?}
 `endif
         );

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -523,7 +523,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         });
     endrule
 
-`ifdef RVFI_DII
+`ifdef RVFI
     Vector#(TExp#(SizeOf#(LdStQTag)), Reg#(Data)) memData <- replicateM(mkReg(?));
 `endif
 
@@ -538,9 +538,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         CapPipe data = x.rVal2;
         MemTaggedData toMemData = unpack(pack(toMem(data)));
 
-`ifdef RVFI_DII
+`ifdef RVFI
         memData[pack(x.ldstq_tag)] <= getAddr(data);
-        $display("%t : memData[%x] <= %x", $time(), pack(x.ldstq_tag), getAddr(data));
 `endif
 
         // get shifted data and BE
@@ -856,7 +855,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
 `ifdef RVFI
             LdStQTag idx = tagged Ld tag;
             memData[pack(idx)] <= truncate(pack(res.data)); // TODO use fromMem?
-            $display("%t : memData[%x] <= %x", $time(), pack(idx), res.data);
 `endif
         end
         if(res.wrongPath) begin

src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv

@@ -732,7 +732,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
                 doAssert((dInst.iType != Fence) == isValid(dInst.imm),
                          "Mem (non-Fence) needs imm for virtual addr");
                 Bit#(16) dum = hash(getAddr(pc));
-                $display("pc : %x , hash(pc) : %x", pc, dum);
                 // put in ldstq
                 if(isLdQ) begin
                     lsq.enqLd(inst_tag, mem_inst, allow_cap, phy_regs.dst, spec_bits, hash(getAddr(pc)));
@@ -1073,7 +1072,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
                                 doAssert(!isValid(spec_tag), "should not have spec tag");
                                 // put in ldstq
                                 Bit#(16) dum = hash(getAddr(pc));
-                                $display("pc : %x , hash(pc) : %x", pc, dum);
                                 if(isLdQ) begin
                                     lsq.enqLd(inst_tag, mem_inst, phy_regs.dst, spec_bits, hash(getAddr(pc)));
                                 end

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -287,10 +287,11 @@ module mkDTlb#(
         end
         else if(pRs.entry matches tagged Valid .en) begin
             // check permission
-            $display("dPRs: vm_info: ", fshow(vm_info),
-                     "      en     : ", fshow(en),
-                     "      r      : ", fshow(r)
-                     );
+            if (verbose)
+                $display("dPRs: vm_info: ", fshow(vm_info),
+                         "      en     : ", fshow(en),
+                         "      r      : ", fshow(r)
+                         );
             let permCheck = hasVMPermission(vm_info,
                                             en.pteType,
                                             en.pteUpperType,

src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv

@@ -46,7 +46,7 @@ import MemoryTypes::*;
 import CHERICap::*;
 import CHERICC_Fat::*;
 import ISA_Decls_CHERI::*;
-`ifdef RVFI_DII
+`ifdef RVFI
 import GetPut::*;
 import RVFI_DII_Types::*;
 `endif
@@ -86,8 +86,10 @@ typedef struct {
 `endif
 } InstTag deriving(Bits, Eq, FShow);
 
-`ifdef RVFI_DII
+`ifdef RVFI
 typedef Vector#(SupSize, Maybe#(RVFI_DII_Execution #(64, 64))) Rvfi_Traces;
+`endif
+`ifdef RVFI_DII
 typedef Vector#(TMul#(SupSize, 2), RVFI_DII_Parcel_Resp) Dii_Parcel_Resps;
 typedef Vector#(TMul#(SupSize, 2), Bit#(16)) Dii_Parcels;
 

src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv

@@ -756,7 +756,6 @@ module mkSupReorderBuffer#(
                 // move deqP & reset valid
                 deqP[i] <= getNextPtr(deqP[i]);
                 valid[i][deqP[i]][valid_deq_port] <= False;
-                $display("deq[%d][%d]", i, deqP[i]);
             end
         end
         // update firstDeqWay: find the first deq port that is not enabled