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Implement x0 default value in the memory pipe.

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jon
2020-05-11 12:21:57 +01:00
parent cf39ec8368
commit 6e00bd627b
1 changed files with 4 additions and 4 deletions
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8
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -423,14 +423,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
let regsReady = inIfc.sbCons_lazyLookup(x.regs);
// get rVal1 (check bypass)
CapPipe rVal1 = ?;
if(x.regs.src1 matches tagged Valid .src1) begin
CapPipe rVal1 = nullCap;
if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
end
// get rVal2 (check bypass)
CapPipe rVal2 = ?;
if(x.regs.src2 matches tagged Valid .src2) begin
CapPipe rVal2 = nullCap;
if(x.regs.src2 matches tagged Valid .src2 &&& src2 != 0) begin
rVal2 <- readRFBypass(src2, regsReady.src2, inIfc.rf_rd2(src2), bypassWire);
end