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Update Tesbench toplevel interface sizes

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This commit is contained in:
Alexandre Joannou
2022-08-23 19:04:14 +01:00
parent b3250d4357
commit 6e58006e10
3 changed files with 3 additions and 3 deletions
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2
builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
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@@ -22,7 +22,7 @@ BSC_COMPILATION_FLAGS += \
-D FABRIC64 \
-D CheriBusBytes=8 \
-D CheriMasterIDWidth=1 \
-D CheriTransactionIDWidth=5 \
-D CheriTransactionIDWidth=6 \
-D CAP128 -D BLUESIM \
-D MEM64 \
-D RISCV \

2
builds/Resources/Include_Common.mk
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@@ -90,7 +90,7 @@ BSC_COMPILATION_FLAGS += \
-D FABRIC64 \
-D CheriBusBytes=8 \
-D CheriMasterIDWidth=1 \
-D CheriTransactionIDWidth=5 \
-D CheriTransactionIDWidth=6 \
-D CAP128 -D BLUESIM \
-D MEM64 \
-D RISCV \

2
src_Testbench/SoC/SoC_Top.bsv
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@@ -93,7 +93,7 @@ import Debug_Module :: *;
interface SoC_Top_IFC;
`ifdef INCLUDE_GDB_CONTROL
interface AXI4Lite_Slave #(7, 32, 0, 0, 0, 0, 0) debug_subordinate;
interface AXI4Lite_Slave #(21, 32, 0, 0, 0, 0, 0) debug_subordinate;
`endif
`ifdef INCLUDE_TANDEM_VERIF