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Trap on access of fcsr when floating point is not enabled.

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jon
2020-04-02 13:05:42 +01:00
parent 4714070aef
commit 7618c5cec8
1 changed files with 7 additions and 1 deletions
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8
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
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@@ -239,11 +239,15 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
|| isValid (x.regs.src3)
|| fn_ArchReg_is_FpuReg (x.regs.dst));
let mstatus = csrf.rd (CSRmstatus);
Bool fs_trap = ((mstatus [14:13] == 2'b00) && fpr_access);
// Check CSR access permission
Bool csr_access_trap = False;
if (x.dInst.iType == Csr) begin
if (x.dInst.csr matches tagged Valid .c) begin
case (c)
CSRfcsr: fpr_access = True;
endcase
end
Bit #(12) csr_addr = case (x.dInst.csr) matches
tagged Valid .c: pack (c);
default: 12'hCFF;
@@ -264,6 +268,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
csr_access_trap = (write_deny || priv_deny || unimplemented);
end
Bool fs_trap = ((mstatus [14:13] == 2'b00) && fpr_access);
// Check WFI trap (using a time-out of 0)
Bit #(32) inst_WFI = 32'h_1050_0073;
Bit #(1) mstatus_tw = mstatus [21];