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Reduce "verbosity".

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This commit is contained in:
Jonathan Woodruff
2020-03-12 10:47:07 +00:00
parent 41fd6b2b60
commit 79935d848f
4 changed files with 8 additions and 14 deletions
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10
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -318,8 +318,8 @@ module mkFetchStage(FetchStage);
// rule ordering: Fetch1 (BTB+TLB) < Fetch3 (decode & dir pred) < redirect method
// Fetch1 < Fetch3 to avoid bypassing path on PC and epochs
Bool verbose = True;
Integer verbosity = 1;
Bool verbose = False;
Integer verbosity = 0;
// Basic State Elements
Reg#(Bool) started <- mkReg(False);
@@ -430,12 +430,6 @@ module mkFetchStage(FetchStage);
//dii_instIds.enq(reqs);
//dii_id_next <= next_id + `sizeSup;
//endrule
Reg#(Bit#(4)) ticker <- mkReg(0);
rule tick;
ticker <= ticker + 1;
if (ticker == 0) $display("%t : tick", $time);
endrule
`endif
// Predict the next fetch-PC based only on current PC (without

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -188,7 +188,7 @@ interface MemExePipeline;
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
Bool verbose = True;
Bool verbose = False;
// we change cache request in case of single core, becaues our MSI protocol
// is not good with single core

8
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
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@@ -251,7 +251,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= PPC (cf.nextPc);
end
`ifdef RVFI
$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
//$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
traceBundle[pvc_finishAlu_port(i)] <= tb;
`endif
doAssert(isValid(csr) == isValid(csrData), "csr valid should match");
@@ -294,7 +294,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
// update VAddr
ppc_vaddr_csrData[pvc_finishMem_port] <= VAddr (vaddr);
`ifdef RVFI
$display("%t : traceBundle = ", $time(), fshow(tb), " in setExecuted_doFinishMem for %x", pc);
//$display("%t : traceBundle = ", $time(), fshow(tb), " in setExecuted_doFinishMem for %x", pc);
traceBundle[pvc_finishMem_port] <= tb;
`endif
// update access at commit
@@ -340,7 +340,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
diid <= x.diid;
`endif
`ifdef RVFI
$display("%t : traceBundle = ", $time(), fshow(x.traceBundle), " in write_enq for %x", pc);
//$display("%t : traceBundle = ", $time(), fshow(x.traceBundle), " in write_enq for %x", pc);
traceBundle[pvc_enq_port] <= x.traceBundle;
`endif
// check
@@ -402,7 +402,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
rob_inst_state[state_deqLSQ_port] <= Executed;
`ifdef RVFI
traceBundleMem <= tb;
$display("%t: Wrote tb for deqLSQ ", $time(), fshow(tb));
//$display("%t: Wrote tb for deqLSQ ", $time(), fshow(tb));
`endif
// record trap
doAssert(!isValid(trap[trap_deqLSQ_port]), "cannot have trap");

2
src_Verifier/Toooba_RVFI_DII_Bridge.bsv
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@@ -69,7 +69,7 @@ module mkTooobaRVFIDIIBridge(Toooba_RVFI_DII_Bridge_IFC);
FIFO#(Dii_Ids) seq_req <- mkFIFO;
Reg#(Dii_Id) last_id <- mkReg(0);
Bool verbose = True;
Bool verbose = False;
function Bool validReport(RVFI_DII_Execution#(DataSz,DataSz) trace);
return (trace.rvfi_insn != dii_nop);