Delay returns (up to 10 cycles) if there is an outstanding push.
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@@ -55,7 +55,6 @@ typedef RasIndex RasPredTrainInfo;
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interface ReturnAddrStack;
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interface Vector#(SupSize, RAS) ras;
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method Action willPush;
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method Bool pendingPush;
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method Action push(CapMem pushAddr);
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method Action write(CapMem pushAddr, RasIndex h);
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@@ -67,10 +66,20 @@ endinterface
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(* synthesize *)
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module mkRas(ReturnAddrStack) provisos(NumAlias#(TExp#(TLog#(RasEntries)), RasEntries));
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Vector#(RasEntries, Ehr#(2, CapMem)) stack <- replicateM(mkEhr(nullCap));
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Vector#(RasEntries, Ehr#(3, Bool)) valids <- replicateM(mkEhr(False));
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// head points past valid data
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// to gracefully overflow, head is allowed to overflow to 0 and overwrite the oldest data
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Ehr#(TAdd#(SupSize, 3), RasIndex) head <- mkEhr(0);
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Bool invalidHead = !(valids[head[0]][0]);
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Reg#(Bit#(6)) delay <- mkReg(0);
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rule resetValidHead(invalidHead);
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if (delay < 10) delay <= delay + 1;
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else begin
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valids[head[0]][2] <= True;
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delay <= 0;
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end
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endrule
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`ifdef SECURITY
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Reg#(Bool) flushDone <- mkReg(True);
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@@ -97,10 +106,11 @@ module mkRas(ReturnAddrStack) provisos(NumAlias#(TExp#(TLog#(RasEntries)), RasEn
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endinterface);
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end
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method Bool pendingPush = False;//(pendingPushReg[0] > 0 && pendingPushDelay < 6);
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method Bool pendingPush = invalidHead;
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method Action push(CapMem pushAddr);
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Reg#(RasIndex) h = head[valueof(SupSize) + 2];
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valids[h+1][0] <= False;
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`ifndef NO_SPEC_RSB_PUSH
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stack[h+1][1] <= pushAddr;
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$display("RAS push stack[%d] <- %x", h+1, pushAddr);
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@@ -111,6 +121,7 @@ module mkRas(ReturnAddrStack) provisos(NumAlias#(TExp#(TLog#(RasEntries)), RasEn
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method Action write(CapMem pushAddr, RasIndex h);
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stack[h][1] <= pushAddr;
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valids[h][1] <= True;
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$display("RAS write stack[%d] <- %x", h, pushAddr);
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endmethod
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