Cheri-research/Toooba
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Remove commented-out code.

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jon
2020-07-13 18:20:56 +01:00
parent f638644b84
commit 83b734ed87
1 changed files with 0 additions and 9 deletions
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9
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -645,10 +645,6 @@ module mkFetchStage(FetchStage);
default: begin
// Access fault
cause = Valid (InstAccessFault);
// Without 'C' extension:
// Addr align32b_mask = 'h3;
// Addr align16b_mask = 'h1;
// tval = (getAddr(in.pc) & (~ align16b_mask));
`ifdef DEBUG_WEDGE
lastImemReq <= 'hafafafafafafafaf;
`endif
@@ -657,11 +653,6 @@ module mkFetchStage(FetchStage);
end
else begin
// TLB exception: record the request address
// Without 'C' extension:
// Addr align32b_mask = 'h3;
// tval = (in.pc & (~ align32b_mask));
// Addr align16b_mask = 'h1;
// tval = (getAddr(in.pc) & (~ align16b_mask));
`ifdef DEBUG_WEDGE
lastImemReq <= 'heeeeeeeeeeeeeeee;
`endif