Cheri-research/Toooba
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Remove tval from the reorder buffer and just use PC.

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It's currently unknown to me what the function of tval in the reorder
buffer was, which is a bit scary.
It seemed to have some additional calculation to do with instruction
alignment, but verification with compressed instructions still seems to
work.
This commit is contained in:
jon
2020-07-13 18:11:13 +01:00
parent 6d4b00c865
commit f638644b84
5 changed files with 22 additions and 43 deletions
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4
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -205,8 +205,8 @@ interface AluExePipeline;
endinterface
module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
Bool verbose = True;
Integer verbosity = 2;
Bool verbose = False;
Integer verbosity = 0;
// alu reservation station
ReservationStationAlu rsAlu <- mkReservationStationAlu;

4
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -646,10 +646,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if(verbose) $display("[doCommitTrap] ", fshow(x));
// record trap info
Addr vaddr = ?;
Addr vaddr = 0;
if ( (trap == tagged Exception InstAccessFault)
|| (trap == tagged Exception InstPageFault)) begin
vaddr = x.tval;
vaddr = getAddr(x.pc);
end
else if(x.ppc_vaddr_csrData matches tagged VAddr .va) begin
vaddr = getAddr(va);

35
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
View File

@@ -156,7 +156,6 @@ typedef struct {
CapMem pc;
Maybe#(CapMem) pred_next_pc;
Maybe#(Exception) cause;
Addr tval; // in case of exception
Bool access_mmio; // inst fetch from MMIO
Bool fetch3_epoch;
Bool decode_epoch;
@@ -167,7 +166,6 @@ typedef struct {
CapMem pred_next_pc;
Bool mispred_first_half;
Maybe#(Exception) cause;
Addr tval; // in case of exception
Bool decode_epoch;
Epoch main_epoch;
} Fetch3ToDecode deriving(Bits, Eq, FShow);
@@ -192,7 +190,6 @@ typedef struct {
Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b)
ArchRegs regs;
Maybe#(Exception) cause;
Addr tval; // in case of exception
`ifdef RVFI_DII
Dii_Id diid;
`endif
@@ -382,13 +379,16 @@ function ActionValue #(Tuple4 #(SupCntX2,
pc = next_pc;
end
`else
Addr increment = 0;
for (Integer i = 0; i < valueOf(SupSize); i = i + 1) begin
Bit #(32) inst = { v_x16 [(2*i)+1], v_x16 [2*i] };
v_items[i].inst_kind = Inst_32b;
Bool compressed = is_16b_inst (v_x16 [2*i]);
v_items[i].inst_kind = compressed ? Inst_16b:Inst_32b;
increment = increment + (compressed ? 2:4);
v_items[i].orig_inst = inst;
v_items[i].inst = inst;
v_items[i].inst = (compressed) ? fv_decode_C (misa, misa_mxl_64, v_x16 [2*i]):inst;
end
pc = getAddr(pc_start) + 8;
pc = getAddr(pc_start) + increment;
n_items = 2;
`endif
@@ -617,7 +617,6 @@ module mkFetchStage(FetchStage);
// Get TLB response
match {.phys_pc, .cause} <- tlb_server.response.get;
Addr tval = 0;
// Access main mem or boot rom if no TLB exception
Bool access_mmio = False;
@@ -648,9 +647,8 @@ module mkFetchStage(FetchStage);
cause = Valid (InstAccessFault);
// Without 'C' extension:
// Addr align32b_mask = 'h3;
// tval = (in.pc & (~ align32b_mask));
Addr align16b_mask = 'h1;
tval = (getAddr(in.pc) & (~ align16b_mask));
// Addr align16b_mask = 'h1;
// tval = (getAddr(in.pc) & (~ align16b_mask));
`ifdef DEBUG_WEDGE
lastImemReq <= 'hafafafafafafafaf;
`endif
@@ -662,8 +660,8 @@ module mkFetchStage(FetchStage);
// Without 'C' extension:
// Addr align32b_mask = 'h3;
// tval = (in.pc & (~ align32b_mask));
Addr align16b_mask = 'h1;
tval = (getAddr(in.pc) & (~ align16b_mask));
// Addr align16b_mask = 'h1;
// tval = (getAddr(in.pc) & (~ align16b_mask));
`ifdef DEBUG_WEDGE
lastImemReq <= 'heeeeeeeeeeeeeeee;
`endif
@@ -674,7 +672,6 @@ module mkFetchStage(FetchStage);
pc: in.pc,
pred_next_pc: in.pred_next_pc,
cause: cause,
tval: tval,
access_mmio: access_mmio,
fetch3_epoch: in.fetch3_epoch,
decode_epoch: in.decode_epoch,
@@ -805,7 +802,6 @@ module mkFetchStage(FetchStage);
pred_next_pc: pred_next_pc,
mispred_first_half: mispred_first_half,
cause: fetch3In.cause,
tval: fetch3In.tval,
decode_epoch: fetch3In.decode_epoch,
main_epoch: fetch3In.main_epoch
};
@@ -854,7 +850,6 @@ module mkFetchStage(FetchStage);
pred_next_pc: out.pred_next_pc,
mispred_first_half: False,
cause: tagged Invalid,
tval: 0,
decode_epoch: out.decode_epoch,
main_epoch: out.main_epoch
};
@@ -927,7 +922,6 @@ module mkFetchStage(FetchStage);
cause: decodeIn.cause
};
let cause = in.cause;
Addr tval = decodeIn.tval;
if (verbose)
$display("Decode: %0d in = ", i, fshow (in));
@@ -938,10 +932,9 @@ module mkFetchStage(FetchStage);
let decode_result = decode(in.inst, getFlags(inst_data[i].pc)==1); // Decode 32b inst, or 32b expansion of 16b inst
// update cause and tval if decode exception and no earlier (TLB) exception
// update cause if decode exception and no earlier (TLB) exception
if (!isValid(cause)) begin
cause = decode_result.illegalInst ? tagged Valid IllegalInst : tagged Invalid;
tval = decodeIn.tval;
end
let dInst = decode_result.dInst;
@@ -1042,11 +1035,11 @@ module mkFetchStage(FetchStage);
dInst: dInst,
orig_inst: inst_data[i].orig_inst,
regs: decode_result.regs,
cause: cause,
cause: cause
`ifdef RVFI_DII
diid: fromMaybe(?,ids[i]),
, diid: fromMaybe(?,ids[i])
`endif
tval: tval};
};
out_fifo.enqS[i].enq(out);
if (verbosity >= 1) begin
$write ("%0d: %m.rule doDecode: out_fifo.enqS[%0d].enq", cur_cycle, i);

4
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
View File

@@ -337,7 +337,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
let dInst = x.dInst;
let arch_regs = x.regs;
let cause = x.cause;
let tval = x.tval;
if(verbose) $display("[doRenaming] trap: ", fshow(x));
@@ -360,7 +359,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
scr: dInst.scr,
claimed_phy_reg: False, // no renaming is done
trap: firstTrap,
tval: tval,
// default values of FullResult
ppc_vaddr_csrData: PPC (cast(pc)), // default use PPC
fflags: 0,
@@ -561,7 +559,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
scr: dInst.scr,
claimed_phy_reg: True, // XXX we always claim a free reg in rename
trap: Invalid, // no trap
tval: 0,
// default values of FullResult
ppc_vaddr_csrData: PPC (cast(ppc)), // default use PPC
fflags: 0,
@@ -1104,7 +1101,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
scr: dInst.scr,
claimed_phy_reg: True, // XXX we always claim a free reg in rename
trap: Invalid, // no trap
tval: 0,
// default values of FullResult
ppc_vaddr_csrData: PPC (cast(ppc)), // default use PPC
fflags: 0,

18
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -88,7 +88,6 @@ typedef struct {
Maybe#(CSR) csr;
Bool claimed_phy_reg; // whether we need to commmit renaming
Maybe#(Trap) trap;
Addr tval; // in case of trap
PPCVAddrCSRData ppc_vaddr_csrData;
Bit#(5) fflags;
Bool will_dirty_fpu_state; // True means 2'b11 will be written to FS
@@ -266,7 +265,6 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
Reg#(Maybe#(SCR)) scr <- mkRegU;
Reg#(Bool) claimed_phy_reg <- mkRegU;
Ehr#(TAdd#(TAdd#(2, TDiv#(aluExeNum,2)), aluExeNum), Maybe#(Trap)) trap <- mkEhr(?);
Ehr#(TAdd#(TAdd#(2, TDiv#(aluExeNum,2)), aluExeNum), Addr) tval <- mkEhr(?);
Ehr#(TAdd#(2, aluExeNum), PPCVAddrCSRData) ppc_vaddr_csrData <- mkEhr(?);
Ehr#(TAdd#(1, fpuMulDivExeNum), Bit#(5)) fflags <- mkEhr(?);
Reg#(Bool) will_dirty_fpu_state <- mkRegU;
@@ -314,17 +312,14 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
// update PPC or csrData (vaddr is always useless for ALU results)
ppc_vaddr_csrData[pvc_finishAlu_port(i)] <= csrDataOrPPC;
if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishAlu_port(i)])) begin
if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishAlu_port(i)]))
trap[trap_finishAlu_port(i)] <= Valid (CapException (exp));
tval[trap_finishAlu_port(i)] <= tval[trap_finishAlu_port(i)];
end
`ifdef RVFI
//$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
traceBundle[trap_finishAlu_port(i)] <= tb;
`endif
Bool isCsrData = False;
if (csrDataOrPPC matches tagged CSRData .unused) isCsrData = True;
doAssert((isValid(csr) || isValid(scr)) == isCsrData, "csr valid should match");
if (csrDataOrPPC matches tagged CSRData .unused)
doAssert((isValid(csr) || isValid(scr)), "Either a csr write or an scr write is expected if we receive valid CSRData");
endmethod
endinterface);
end
@@ -349,10 +344,8 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
`endif
// update fflags
fflags[fflags_finishFpuMulDiv_port(i)] <= new_fflags;
if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishFpuMulDiv_port(i)])) begin
if (cause matches tagged Valid .exp &&& !isValid(trap[trap_finishFpuMulDiv_port(i)]))
trap[trap_finishFpuMulDiv_port(i)] <= Valid (Exception (exp));
tval[trap_finishFpuMulDiv_port(i)] <= tval[trap_finishAlu_port(i)];
end
`ifdef RVFI
//$display("%t : traceBundle = ", $time(), fshow(tb), " in Row_setExecuted_doFinishAlu for %x", pc);
traceBundle[trap_finishFpuMulDiv_port(i)] <= tb;
@@ -427,7 +420,6 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
scr <= x.scr;
claimed_phy_reg <= x.claimed_phy_reg;
trap[trap_enq_port] <= x.trap;
tval[trap_enq_port] <= x.tval;
ppc_vaddr_csrData[pvc_enq_port] <= x.ppc_vaddr_csrData;
fflags[fflags_enq_port] <= x.fflags;
will_dirty_fpu_state <= x.will_dirty_fpu_state;
@@ -474,7 +466,6 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
scr: scr,
claimed_phy_reg: claimed_phy_reg,
trap: trap[trap_deq_port],
tval: tval[trap_deq_port],
ppc_vaddr_csrData: ppc_vaddr_csrData[pvc_deq_port],
fflags: fflags[fflags_deq_port],
will_dirty_fpu_state: will_dirty_fpu_state,
@@ -523,7 +514,6 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
// record trap
//doAssert(!isValid(trap[trap_deqLSQ_port]), "cannot have trap");
if(isValid(cause)) trap[trap_deqLSQ_port] <= cause;
// TODO: shouldn't we record tval here as well?
// record ld misspeculation
ldKilled[ldKill_deqLSQ_port] <= ld_killed;
endmethod