Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Another experiment to see if we can resolve the vcu118 build.

Browse Source 
This one puts the in-order shim before the width converter.
This commit is contained in:
Jonathan Woodruff
2024-04-05 10:54:39 +01:00
parent 8990ae56ed
commit 854e8e5bfb
2 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src_SSITH_P3/src_BSV/P3_Core.bsv
View File

@@ -177,7 +177,8 @@ module mkP3_Core (P3_Core_IFC);
, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) )
wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth);
match {.wideS, .narrowM} = wideS_narrowM;
mkConnection(corew.manager_0, wideS);
let master0_inOrder <- mkAXI4SingleIDMaster(corew.manager_0);
mkConnection(master0_inOrder, wideS);
// ================================================================
// Delay DRAM to compensate for relatively lower FPGA clock

3
src_Testbench/SoC/SoC_Top.bsv
View File

@@ -169,7 +169,8 @@ module mkSoC_Top #(Reset dm_power_on_reset)
, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) )
wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth);
match {.wideS, .narrowM} = wideS_narrowM;
mkConnection(corew.manager_0, wideS);
let master0_inOrder <- mkAXI4SingleIDMaster(corew.manager_0);
mkConnection(master0_inOrder, wideS);
// SoC IPs
UART_IFC uart0 <- mkUART;