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Revert "Potential workaround for issue with vcu118 memory bus error."

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This reverts commit f86ea0203d.
This commit is contained in:
Jonathan Woodruff
2024-04-05 10:44:50 +01:00
parent f86ea0203d
commit 8990ae56ed
1 changed files with 1 additions and 5 deletions
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6
src_SSITH_P3/src_BSV/P3_Core.bsv
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@@ -340,13 +340,9 @@ module mkP3_Core (P3_Core_IFC);
// ================================================================
`endif
// Work around issue that is not understood with multiple outstanding
// requests in VCU118 GFE system.
let master0_inOrder <- mkAXI4SingleIDMaster(master_0_delay.master);
// ================================================================
// INTERFACE
let master0_sig <- toAXI4_Master_Sig (master0_inOrder);
let master0_sig <- toAXI4_Master_Sig (master_0_delay.master);
let master1_sig <- toAXI4_Master_Sig (master_1_delay.master);
// ----------------------------------------------------------------
// Core CPU interfaces