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FetchStage.bsv: Fix a mkRegU that should be a mkReg

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We should not use a mkRegU for rg_pending_n_items, as otherwise there is
a chance the epochs for rg_pending_f32d happen to match depending on the
uninitialised values. Instead ensure we always reset with no pending
items.
This commit is contained in:
Jessica Clarke
2020-04-08 04:21:13 +01:00
parent 9e72052437
commit 85b4a738a9
1 changed files with 1 additions and 1 deletions
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src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -390,7 +390,7 @@ module mkFetchStage(FetchStage);
Ehr #(2, Maybe #(Tuple3 #(Addr, Bit #(16), Bool))) ehr_pending_straddle <- mkEhr(tagged Invalid);
// Reg to hold extra instructions from Fetch3 to send to decode the next cycle
Reg #(Vector #(SupSizeX2S1, Inst_Item)) rg_pending_decode <- mkReg(replicate(defaultValue));
Reg #(SupCntX2S1) rg_pending_n_items <- mkRegU;
Reg #(SupCntX2S1) rg_pending_n_items <- mkReg(0);
Reg #(Fetch3ToDecode) rg_pending_f32d <- mkRegU;
// Pipeline Stage FIFOs