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Merge remote-tracking branch 'upstream/master' into CHERI

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This commit is contained in:
Peter Rugg
2020-06-17 13:01:41 +01:00
parent 49a9e5fc64 db0e357475
commit 8778369fe5
28 changed files with 1494 additions and 542 deletions
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7
src_Core/CPU/Core.bsv
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@@ -114,6 +114,7 @@ import Trace_Data2 :: *;
interface CoreReq;
method Action start(
Bool running,
Addr startpc,
Addr toHostAddr, Addr fromHostAddr
);
@@ -1237,7 +1238,9 @@ module mkCore#(CoreId coreId)(Core);
// Debugger 'halt' request (e.g., GDB '^C' command)
// This is initiated just like an interrupt.
`ifdef INCLUDE_GDB_CONTROL
renameStage.debug_halt_req;
`endif
if (show_DM_interactions)
$display ("%0d: %m.rl_debug_halt_req", cur_cycle);
@@ -1327,9 +1330,13 @@ module mkCore#(CoreId coreId)(Core);
interface CoreReq coreReq;
method Action start(
Bool running,
Bit#(64) startpc,
Addr toHostAddr, Addr fromHostAddr
);
`ifdef INCLUDE_GDB_CONTROL
if (!running) renameStage.debug_halt_req;
`endif
fetchStage.start(setAddrUnsafe(almightyCap, startpc)
`ifdef RVFI_DII
, 0

14
src_Core/CPU/MMIOPlatform.bsv
View File

@@ -193,6 +193,10 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
// CRs, we record the AMO resp at processing time
Reg#(MemTaggedData) amoResp <- mkRegU;
// For AMOs to the fabric, we end up with read and write responses, and need
// to discard the latter. This tracks which of the two we're waiting for.
Reg#(Bool) amoWaitWriteResp <- mkRegU;
// we increment mtime periodically
Reg#(Bit#(TLog#(CyclesPerTimeInc))) cycle <- mkReg(0);
@@ -836,6 +840,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
let req = MMIOCRq {addr:addr, func:tagged Ld, byteEn:?, data:?};
mmio_fabric_adapter_core_side.request.put (req);
state <= WaitResp;
amoWaitWriteResp <= False;
if (verbosity > 0) begin
$display ("MMIOPlatform.rl_mmio_to_fabric_amo_req: addr 0x%0h", addr);
@@ -849,7 +854,11 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
&&& isAmo);
MMIODataPRs dprs <- mmio_fabric_adapter_core_side.response.get;
if (! dprs.valid) begin
if (amoWaitWriteResp) begin
// Discard the write response; we're now ready for another request
state <= SelectReq;
end
else if (! dprs.valid) begin
// Access fault
let prs = tagged DataAccess dprs;
cores[reqCore].pRs.enq (prs);
@@ -875,7 +884,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
let prs = tagged DataAccess (MMIODataPRs { valid: True, data: ld_val });
cores[reqCore].pRs.enq (prs);
state <= SelectReq;
// Stay in WaitResp but wait to discard the write response
amoWaitWriteResp <= True;
if (verbosity > 1) begin
$display ("MMIO_Platform.rl_mmio_from_fabric_amo_rsp: addr 0x%0h, size %0d, amofunc %0d",

4
src_Core/CPU/Proc.bsv
View File

@@ -233,10 +233,10 @@ module mkProc (Proc_IFC);
// ----------------
// Start the cores running
// Use toHostAddr = 0 if not monitoring tohost
method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr);
method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr);
action
for(Integer i = 0; i < valueof(CoreNum); i = i+1)
core[i].coreReq.start (startpc, tohostAddr, fromhostAddr);
core[i].coreReq.start (running, startpc, tohostAddr, fromhostAddr);
endaction
mmioPlatform.start (tohostAddr, fromhostAddr);

2
src_Core/CPU/Proc_IFC.bsv
View File

@@ -43,7 +43,7 @@ interface Proc_IFC;
// ----------------
// Start the cores running
// Use toHostAddr = 0 if not monitoring tohost
method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr);
method Action start (Bool running, Addr startpc, Addr tohostAddr, Addr fromhostAddr);
// ----------------
// SoC fabric connections

7
src_Core/Core/CoreW.bsv
View File

@@ -200,9 +200,8 @@ module mkCoreW #(Reset dm_power_on_reset)
rule rl_dm_hart0_reset_wait (rg_hart0_reset_delay != 0);
if (rg_hart0_reset_delay == 1) begin
let pc = soc_map_struct.pc_reset_value;
proc.start (pc, rg_tohost_addr, rg_fromhost_addr);
Bool is_running = True;
proc.start (is_running, pc, rg_tohost_addr, rg_fromhost_addr);
debug_module.hart0_reset_client.response.put (is_running);
$display ("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h",
cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr);
@@ -398,12 +397,12 @@ module mkCoreW #(Reset dm_power_on_reset)
// ----------------------------------------------------------------
// Start
method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base),
zeroExtend (rangeTop(soc_map.m_plic_addr_range)));
let pc = soc_map_struct.pc_reset_value;
proc.start (pc, tohost_addr, fromhost_addr);
proc.start (is_running, pc, tohost_addr, fromhost_addr);
`ifdef INCLUDE_GDB_CONTROL
// Save for potential future use by rl_dm_hart0_reset

2
src_Core/Core/CoreW_IFC.bsv
View File

@@ -61,7 +61,7 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources);
// ----------------------------------------------------------------
// Start
method Action start (Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
// ----------------------------------------------------------------
// AXI4 Fabric interfaces

15
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
View File

@@ -144,7 +144,6 @@ typedef struct {
} Fetch2ToFetch3 deriving(Bits, Eq, FShow);
typedef struct {
CapMem pc;
CapMem pred_next_pc;
Bool mispred_first_half;
Maybe#(Exception) cause;
@@ -296,8 +295,8 @@ function ActionValue #(Tuple4 #(SupCntX2,
orig_inst: 0,
inst: 0});
MStraddle next_straddle = tagged Invalid;
// Start parse at parcel 0/1 depending on pc lsbs and pending straddle
SupCntX2 j = ((getAddr(pc_start) [1:0] == 2'b00 || isValid(pending_straddle)) ? 0 : 1);
// Start parse at parcel 0/1 depending on pc lsbs.
SupCntX2 j = (getAddr(pc_start) [1:0] == 2'b00 ? 0 : 1);
`ifdef RVFI_DII
j = 0;
`endif
@@ -317,10 +316,10 @@ function ActionValue #(Tuple4 #(SupCntX2,
end
pc = getAddr(s_pc);
inst_kind = Inst_32b;
orig_inst = { v_x16[0], s_lsbs };
orig_inst = { v_x16[j], s_lsbs };
inst = orig_inst;
j = 1;
next_pc = getAddr(s_pc) + 4;
j = j + 1;
next_pc = getAddr(s_pc) + 4;
n_items = 1;
end
else if (is_16b_inst (v_x16 [j])) begin
@@ -427,7 +426,7 @@ module mkFetchStage(FetchStage);
Ehr #(2, MStraddle) ehr_pending_straddle <- mkEhr(tagged Invalid);
// Reg to hold extra instructions from Fetch3 to send to decode the next cycle
Reg #(Vector #(SupSizeX2S1, Inst_Item)) rg_pending_decode <- mkReg(replicate(defaultValue));
Reg #(SupCntX2S1) rg_pending_n_items <- mkRegU;
Reg #(SupCntX2S1) rg_pending_n_items <- mkReg(0);
Reg #(Fetch3ToDecode) rg_pending_f32d <- mkRegU;
// Pipeline Stage FIFOs
@@ -763,7 +762,6 @@ module mkFetchStage(FetchStage);
if (pending_n_items == 0) begin
out = Fetch3ToDecode {
pc: fetch3In.pc,
pred_next_pc: pred_next_pc,
mispred_first_half: mispred_first_half,
cause: fetch3In.cause,
@@ -813,7 +811,6 @@ module mkFetchStage(FetchStage);
next_pending_n_items = truncate(n_items - fromInteger(valueOf(SupSize)));
rg_pending_decode <= drop(v_items);
rg_pending_f32d <= Fetch3ToDecode {
pc: v_items[valueOf(SupSize)].pc,
pred_next_pc: out.pred_next_pc,
mispred_first_half: False,
cause: tagged Invalid,

14
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
View File

@@ -850,13 +850,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
CapMem fallthrough_pc = addPc(pc, ((orig_inst[1:0] == 2'b11) ? 4 : 2));
`ifdef INCLUDE_GDB_CONTROL
if ((i != 0) && (csrf.dcsr_step_bit == 1'b1)) begin
stop = True;
debug_step = True;
end
`endif
// check for wrong path, if wrong path, don't process it, leave to the other rule in next cycle
if(!epochManager.checkEpoch[i].check(main_epoch)) begin
stop = True;
@@ -1124,6 +1117,13 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
if(spec_tag matches tagged Valid .t) begin
spec_bits = spec_bits | (1 << t);
end
`ifdef INCLUDE_GDB_CONTROL
if ((i == 0) && (csrf.dcsr_step_bit == 1'b1)) begin
stop = True;
debug_step = True;
end
`endif
end
end
end