Merge branch 'CHERI' of github.com:CTSRD-CHERI/Toooba into CHERI

This commit is contained in:
Franz Fuchs
2021-09-29 14:23:20 +01:00
2 changed files with 31 additions and 13 deletions

View File

@@ -857,9 +857,6 @@ module mkCore#(CoreId coreId)(Core);
`endif // SELF_INV_CACHE
rule readyToFetch(
`ifdef INCLUDE_GDB_CONTROL
(rg_core_run_state == CORE_RUNNING) &&
`endif
!flush_reservation && !flush_tlbs && !update_vm_info
&& iTlb.flush_done && dTlb.flush_done
`ifdef SECURITY_OR_INCLUDE_GDB_CONTROL
@@ -875,16 +872,19 @@ module mkCore#(CoreId coreId)(Core);
`endif
);
fetchStage.done_flushing();
endrule
`ifdef INCLUDE_GDB_CONTROL
if (commitStage.is_debug_halted) begin
started <= False;
rg_core_run_state <= CORE_HALTING;
if (verbosity >= 1)
$display ("%0d: %m.rule readyToFetch: halting for debug mode", cur_cycle);
end
`endif
rule readyToHalt(
(rg_core_run_state == CORE_RUNNING) &&
commitStage.is_debug_halted
);
started <= False;
rg_core_run_state <= CORE_HALTING;
if (verbosity >= 1)
$display ("%0d: %m.rule readyToHalt: halting for debug mode", cur_cycle);
endrule
`endif
`ifdef PERF_COUNT
// incr cycle count

View File

@@ -81,7 +81,9 @@ BLUESTUFF_DIRS = $(REPO)/libs/BlueStuff:$(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/
TAGCONTROLLER_DIRS = $(REPO)/libs/TagController/TagController:$(REPO)/libs/TagController/TagController/CacheCore
BSC_PATH = -p $(CONTRIB_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):src_BSV:$(BLUESTUFF_DIRS):$(TAGCONTROLLER_DIRS):+
RISCV_HPM_Events_DIR = $(REPO)/libs/RISCV_HPM_Events
BSC_PATH = -p $(CONTRIB_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):src_BSV:$(BLUESTUFF_DIRS):$(TAGCONTROLLER_DIRS):$(RISCV_HPM_Events_DIR):+
# ----------------
# Top-level file and module
@@ -111,8 +113,24 @@ src_BSV/TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py
@echo "INFO: Re-generating CHERI tag controller parameters"
$^ -v -c $(CAPSIZE) -s $(TAGS_STRUCT:"%"=%) -a $(TAGS_ALIGN) --data-store-base-addr 0xc0000000 -b $@ 0xbfff8000 0x17ffff000
@echo "INFO: Re-generated CHERI tag controller parameters"
compile_sim: tagsparams
compile_synth: tagsparams
.PHONY: generate_hpm_vector
generate_hpm_vector: GenerateHPMVector.bsv
GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py
@echo "INFO: Re-generating GenerateHPMVector bluespec file"
$^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -b $@
@echo "INFO: Re-generated GenerateHPMVector bluespec file"
.PHONY: stat_counters
stat_counters: StatCounters.bsv
StatCounters.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py
@echo "INFO: Re-generating HPM events struct bluepsec file"
$^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -s $@
@echo "INFO: Re-generated HPM events struct bluespec file"
compile_sim: tagsparams stat_counters generate_hpm_vector
compile_synth: tagsparams stat_counters generate_hpm_vector
# ================================================================
# Generate Verilog RTL from BSV sources (needs Bluespec 'bsc' compiler)