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Merge branch 'faf28_hpm_consistency' into CHERI

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This commit is contained in:
Franz Fuchs
2021-09-29 14:04:08 +01:00
parent 9ea66bed86 db9b5c7f54
commit cf8bfdc4a8
9 changed files with 30 additions and 19 deletions
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6
builds/Resources/Include_Common.mk
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@@ -144,7 +144,7 @@ TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py
generate_hpm_vector: GenerateHPMVector.bsv
GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py
@echo "INFO: Re-generating GenerateHPMVector bluespec file"
$^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -b $@
$^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -b $@
@echo "INFO: Re-generated GenerateHPMVector bluespec file"
@@ -152,7 +152,7 @@ GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py
stat_counters: StatCounters.bsv
StatCounters.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py
@echo "INFO: Re-generating HPM events struct bluepsec file"
$^ $(RISCV_HPM_Events_DIR)/counters.yaml Toooba -s $@
$^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -s $@
@echo "INFO: Re-generated HPM events struct bluespec file"
compile: tagsparams #stat_counters generate_hpm_vector
@@ -166,6 +166,6 @@ clean:
.PHONY: full_clean
full_clean: clean
rm -r -f $(SIM_EXE_FILE)* *.log *.vcd *.hex Logs/
rm -f TagTableStructure.bsv GenerateHPMVector.bsv .depends.mk
rm -f TagTableStructure.bsv StatCounters.bsv GenerateHPMVector.bsv .depends.mk
# ================================================================

2
libs/BlueStuff

Submodule libs/BlueStuff updated: a8d270d79a...df2529dd42

2
libs/RISCV_HPM_Events

Submodule libs/RISCV_HPM_Events updated: e3a12815d2...9e345b27e8

2
libs/TagController

Submodule libs/TagController updated: 7c9ac94d1d...99c43e8138

8
src_Core/CPU/Core.bsv
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@@ -212,7 +212,7 @@ interface Core;
`ifdef PERFORMANCE_MONITORING
method Action events_llc(EventsLL events);
method Action events_tgc(EventsCacheCore events);
method Action events_tgc(EventsTGC events);
`endif
endinterface
@@ -1150,7 +1150,7 @@ module mkCore#(CoreId coreId)(Core);
// different fields than the TLB, which makes it safe to combine them
Reg#(EventsLL) events_llc_reg <- mkRegU;
Reg#(EventsCacheCore) events_tgc_reg <- mkRegU;
Reg#(EventsTGC) events_tgc_reg <- mkRegU;
rule report_events;
EventsCore events = unpack(pack(commitStage.events));
events.evt_REDIRECT = zeroExtend(pack(fetchStage.redirect_evt));
@@ -1160,7 +1160,7 @@ module mkCore#(CoreId coreId)(Core);
EventsCore core_evts = unpack(pack(coreFix.memExeIfc.events) | pack(hpm_core_events[0]));
EventsL1I imem_evts = unpack(pack(iMem.events) | pack(iTlb.events));
EventsL1D dmem_evts = unpack(pack(dMem.events) | pack(dTlb.events));
EventsCacheCore tgc_evts = events_tgc_reg;
EventsTGC tgc_evts = events_tgc_reg;
EventsLL llmem_evts = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
Maybe#(EventsTransExe) mab_trans_exe = tagged Invalid;
@@ -1182,7 +1182,7 @@ module mkCore#(CoreId coreId)(Core);
let ev_struct = HPMEvents{mab_EventsCore: tagged Valid core_evts, mab_EventsL1I: tagged Valid imem_evts,
mab_EventsL1D: tagged Valid dmem_evts, mab_EventsLL: tagged Valid llmem_evts,
mab_EventsCacheCore: tagged Valid tgc_evts, mab_EventsTransExe: mab_trans_exe,
mab_EventsTGC: tagged Valid tgc_evts, mab_EventsTransExe: mab_trans_exe,
mab_AXI4_Slave_Events: tagged Invalid, mab_AXI4_Master_Events: tagged Invalid};
let events = generateHPMVector(ev_struct);

2
src_Core/CPU/Proc.bsv
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@@ -179,7 +179,7 @@ module mkProc (Proc_IFC);
endrule
`ifdef PERFORMANCE_MONITORING
Reg#(EventsCacheCore) events_tgc_reg <- mkRegU;
Reg#(EventsTGC) events_tgc_reg <- mkRegU;
rule broadcastPerfEvents;
for(Integer j = 0; j < valueof(CoreNum); j = j+1) begin
core[j].events_llc(llc.events);

2
src_Core/CPU/Proc_IFC.bsv
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@@ -130,7 +130,7 @@ interface Proc_IFC;
`endif
`ifdef PERFORMANCE_MONITORING
method Action events_tgc(EventsCacheCore events);
method Action events_tgc(EventsTGC events);
`endif
endinterface

21
src_Core/Core/CoreW.bsv
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@@ -60,6 +60,7 @@ import GetPut_Aux :: *;
import Routable :: *;
import AXI4 :: *;
import TagControllerAXI :: *;
import CacheCore :: *;
// ================================================================
// Project imports
@@ -178,7 +179,17 @@ module mkCoreW #(Reset dm_power_on_reset)
mkConnection(proc.master0, tagController.slave, reset_by all_harts_reset);
`ifdef PERFORMANCE_MONITORING
rule report_tagController_events;
EventsCacheCore evts = tagController.events;
EventsCacheCore cache_core_evts = tagController.events;
EventsTGC evts = unpack(0);
evts.evt_WRITE = zeroExtend(pack(cache_core_evts.evt_WRITE));
evts.evt_WRITE_MISS = zeroExtend(pack(cache_core_evts.evt_WRITE_MISS));
evts.evt_READ = zeroExtend(pack(cache_core_evts.evt_READ));
evts.evt_READ_MISS = zeroExtend(pack(cache_core_evts.evt_READ_MISS));
evts.evt_EVICT = zeroExtend(pack(cache_core_evts.evt_EVICT));
`ifdef USECAP
evts.evt_SET_TAG_WRITE = zeroExtend(pack(cache_core_evts.evt_SET_TAG_WRITE));
evts.evt_SET_TAG_READ = zeroExtend(pack(cache_core_evts.evt_SET_TAG_READ));
`endif
proc.events_tgc(evts);
endrule
`endif
@@ -499,13 +510,13 @@ endmodule: mkCoreW
module mkCoreW_Synth #(Reset dm_power_on_reset)
(CoreW_IFC_Synth #(N_External_Interrupt_Sources));
let core <- mkCoreW (dm_power_on_reset);
let cpu_imem_master_synth <- toAXI4_Master_Synth (core.cpu_imem_master);
let cpu_dmem_master_synth <- toAXI4_Master_Synth (core.cpu_dmem_master);
let cpu_imem_master_sig <- toAXI4_Master_Sig (core.cpu_imem_master);
let cpu_dmem_master_sig <- toAXI4_Master_Sig (core.cpu_dmem_master);
method set_verbosity = core.set_verbosity;
method start = core.start;
interface cpu_imem_master = cpu_imem_master_synth;
interface cpu_dmem_master = cpu_dmem_master_synth;
interface cpu_imem_master = cpu_imem_master_sig;
interface cpu_dmem_master = cpu_dmem_master_sig;
interface core_external_interrupt_sources = core.core_external_interrupt_sources;
method nmi_req = core.nmi_req;
`ifdef RVFI_DII

4
src_Core/Core/CoreW_IFC.bsv
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@@ -150,11 +150,11 @@ interface CoreW_IFC_Synth #(numeric type t_n_interrupt_sources);
// AXI4 Fabric interfaces
// CPU IMem to Fabric master interface
interface AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0) cpu_imem_master;
// CPU DMem to Fabric master interface
interface AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0) cpu_dmem_master;
// ----------------------------------------------------------------