Set up config for next-2-lines on miss L1I prefetcher

builds/Resources/Include_RISCY_Config.mk

@@ -45,9 +45,9 @@ SIM_LLC_ARBITER_LAT ?=
 # default check cache deadlock and rename error
 CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
-INSTR_PREFETCHER_LOCATION ?= NONE
+INSTR_PREFETCHER_LOCATION ?= L1
 INSTR_PREFETCHER_TYPE ?= NEXT_LINE_ON_MISS
-DATA_PREFETCHER_LOCATION ?= L1
+DATA_PREFETCHER_LOCATION ?= NONE
 DATA_PREFETCHER_TYPE ?= BLOCK
 
 # clk frequency depends on core size

src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv

@@ -54,7 +54,7 @@ endmodule
 
 module mkNextLineOnMissPrefetcher(Prefetcher)
     provisos (
-        NumAlias#(nextLinesOnMiss, 3),
+        NumAlias#(nextLinesOnMiss, 2),
         Alias#(rqCntT, Bit#(TLog#(TAdd#(nextLinesOnMiss, 1))))
     );
     Reg#(Addr) lastMissAddr <- mkReg(0);