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Reduce verbosity.

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jon
2021-03-05 12:11:49 +00:00
parent 39e895ca4e
commit 89f0c3a45f
2 changed files with 2 additions and 2 deletions
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2
src_Core/CPU/MMIOPlatform.bsv
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@@ -162,7 +162,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
provisos (Bits #(Data, 64)); // this module assumes Data is 64-bit wide
Integer verbosity = 2;
Integer verbosity = 0;
// mtimecmp
Vector#(CoreNum, Reg#(Data)) mtimecmp <- replicateM(mkReg(0));

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -239,7 +239,7 @@ interface MemExePipeline;
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
Bool verbose = True;
Bool verbose = False;
// we change cache request in case of single core, becaues our MSI protocol
// is not good with single core