Reduce verbosity.

2021-03-05 12:11:49 +00:00
parent 39e895ca4e
commit 89f0c3a45f
2 changed files with 2 additions and 2 deletions
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -239,7 +239,7 @@ interface MemExePipeline;
 endinterface

 module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
-    Bool verbose = True;
+    Bool verbose = False;

    // we change cache request in case of single core, becaues our MSI protocol
    // is not good with single core