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removed coreW from component.xml

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Alexandre Joannou
2022-08-16 12:44:00 +00:00
parent a4606c6761
commit 95f554dad1
1 changed files with 0 additions and 5 deletions
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5
src_SSITH_P3/xilinx_ip/component.xml
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@@ -2236,11 +2236,6 @@
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../Verilog_RTL/mkCoreW.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../Verilog_RTL/mkTagController.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>