enabled performance counter in CSR register

builds/Resources/Include_RISCY_Config.mk

@@ -112,6 +112,8 @@ BSC_COMPILATION_FLAGS += \
 	-D RISCV \
 	-D TSO_MM \
 	-D RV64 \
+	-D PERF_COUNT \
+	-D PERFORMANCE_MONITORING \
 	-D ISA_PRIV_M  -D ISA_PRIV_S  -D ISA_PRIV_U  \
 	-D SV39 \
 	-D ISA_I  -D ISA_M  -D ISA_A  -D ISA_F  -D ISA_D  -D ISA_FD_DIV  -D ISA_C  \

src_Core/CPU/Core.bsv

@@ -918,6 +918,7 @@ module mkCore#(CoreId coreId)(Core);
     // incr cycle count
     (* fire_when_enabled, no_implicit_conditions *)
     rule incCycleCnt(doStats);
+        $display("calling cycle");
         cycleCnt.incr(1);
     endrule
 

src_Core/CPU/CsrFile.bsv

@@ -330,7 +330,7 @@ interface StatsCsr;
 endinterface
 
 module mkStatsCsr(StatsCsr);
-    Reg#(Bool) doStats <- mkConfigReg(False);
+    Reg#(Bool) doStats <- mkConfigReg(True);
 
     FIFO#(Bool) writeQ <- mkFIFO1;
 

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -233,6 +233,14 @@ module mkDTlb#(
             L1TlbAllMissCycles: (allMissCycles);
             default: (0);
         endcase);
+        // Print the requested counter and its value
+        $display("[doPerf] Request Type: %0d, Value: %0d", t, d);
+
+        // (Optional) More detailed debug info
+        $display("  accessCnt=%0d, missParentCnt=%0d, missParentLat=%0d",
+             accessCnt, missParentCnt, missParentLat);
+        $display("  L1TlbmissPeerCnt=%0d, L1TlbmissPeerLat=%0d, L1TlbhitUnderMissCnt=%0d, L1TlballMissCycles=%0d",
+             missPeerCnt, missPeerLat, hitUnderMissCnt, allMissCycles);
         perfRespQ.enq(PerfResp {
             pType: t,
             data: d