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Potential fix for lockup condition where the (undefined) bits of

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instruction returned for an invalid fetch (that is, with a valid cause)
indicate a 2-fragment instruction but where a second fragment is not
available.
This commit is contained in:
jon
2021-07-07 11:26:34 +01:00
parent db6a91e0fd
commit 994321e527
1 changed files with 1 additions and 1 deletions
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2
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -624,7 +624,7 @@ module mkFetchStage(FetchStage);
doAssert(prev_frag.dii_pid+1 == frag.dii_pid, "Attached fragments with non-contigious DII IDs");
`endif
end
end else if (is_16b_inst(frag.inst_frag)) begin // 16-bit instruction
end else if (is_16b_inst(frag.inst_frag) || isValid(frag.cause)) begin // 16-bit instruction
new_pick = tagged Valid fetch3_2_instC(frag,
fv_decode_C (misa, misa_mxl_64, getFlags(decompressPc(frag.pc))==1, frag.inst_frag),
zeroExtend(frag.inst_frag));